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f28987b76e
This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
6.1 KiB
TableGen
160 lines
6.1 KiB
TableGen
//===- SparcRegisterInfo.td - Sparc Register defs ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the Sparc register file
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//===----------------------------------------------------------------------===//
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class SparcReg<string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "SP";
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}
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class SparcCtrlReg<string n>: Register<n> {
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let Namespace = "SP";
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}
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let Namespace = "SP" in {
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def sub_even : SubRegIndex;
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def sub_odd : SubRegIndex;
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}
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// Registers are identified with 5-bit ID numbers.
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// Ri - 32-bit integer registers
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class Ri<bits<5> num, string n> : SparcReg<n> {
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let Num = num;
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}
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// Rf - 32-bit floating-point registers
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class Rf<bits<5> num, string n> : SparcReg<n> {
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let Num = num;
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}
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// Rd - Slots in the FP register file for 64-bit floating-point values.
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class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
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let Num = num;
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let SubRegs = subregs;
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let SubRegIndices = [sub_even, sub_odd];
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}
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// Control Registers
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def ICC : SparcCtrlReg<"ICC">;
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def FCC : SparcCtrlReg<"FCC">;
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// Y register
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def Y : SparcCtrlReg<"Y">;
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// Integer registers
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def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
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def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
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def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
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def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
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def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
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def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
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def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
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def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
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def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
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def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>;
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def O2 : Ri<10, "O2">, DwarfRegNum<[10]>;
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def O3 : Ri<11, "O3">, DwarfRegNum<[11]>;
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def O4 : Ri<12, "O4">, DwarfRegNum<[12]>;
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def O5 : Ri<13, "O5">, DwarfRegNum<[13]>;
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def O6 : Ri<14, "SP">, DwarfRegNum<[14]>;
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def O7 : Ri<15, "O7">, DwarfRegNum<[15]>;
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def L0 : Ri<16, "L0">, DwarfRegNum<[16]>;
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def L1 : Ri<17, "L1">, DwarfRegNum<[17]>;
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def L2 : Ri<18, "L2">, DwarfRegNum<[18]>;
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def L3 : Ri<19, "L3">, DwarfRegNum<[19]>;
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def L4 : Ri<20, "L4">, DwarfRegNum<[20]>;
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def L5 : Ri<21, "L5">, DwarfRegNum<[21]>;
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def L6 : Ri<22, "L6">, DwarfRegNum<[22]>;
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def L7 : Ri<23, "L7">, DwarfRegNum<[23]>;
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def I0 : Ri<24, "I0">, DwarfRegNum<[24]>;
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def I1 : Ri<25, "I1">, DwarfRegNum<[25]>;
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def I2 : Ri<26, "I2">, DwarfRegNum<[26]>;
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def I3 : Ri<27, "I3">, DwarfRegNum<[27]>;
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def I4 : Ri<28, "I4">, DwarfRegNum<[28]>;
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def I5 : Ri<29, "I5">, DwarfRegNum<[29]>;
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def I6 : Ri<30, "FP">, DwarfRegNum<[30]>;
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def I7 : Ri<31, "I7">, DwarfRegNum<[31]>;
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// Floating-point registers
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def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>;
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def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>;
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def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>;
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def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>;
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def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>;
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def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>;
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def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>;
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def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>;
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def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>;
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def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>;
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def F10 : Rf<10, "F10">, DwarfRegNum<[42]>;
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def F11 : Rf<11, "F11">, DwarfRegNum<[43]>;
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def F12 : Rf<12, "F12">, DwarfRegNum<[44]>;
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def F13 : Rf<13, "F13">, DwarfRegNum<[45]>;
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def F14 : Rf<14, "F14">, DwarfRegNum<[46]>;
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def F15 : Rf<15, "F15">, DwarfRegNum<[47]>;
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def F16 : Rf<16, "F16">, DwarfRegNum<[48]>;
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def F17 : Rf<17, "F17">, DwarfRegNum<[49]>;
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def F18 : Rf<18, "F18">, DwarfRegNum<[50]>;
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def F19 : Rf<19, "F19">, DwarfRegNum<[51]>;
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def F20 : Rf<20, "F20">, DwarfRegNum<[52]>;
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def F21 : Rf<21, "F21">, DwarfRegNum<[53]>;
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def F22 : Rf<22, "F22">, DwarfRegNum<[54]>;
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def F23 : Rf<23, "F23">, DwarfRegNum<[55]>;
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def F24 : Rf<24, "F24">, DwarfRegNum<[56]>;
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def F25 : Rf<25, "F25">, DwarfRegNum<[57]>;
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def F26 : Rf<26, "F26">, DwarfRegNum<[58]>;
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def F27 : Rf<27, "F27">, DwarfRegNum<[59]>;
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def F28 : Rf<28, "F28">, DwarfRegNum<[60]>;
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def F29 : Rf<29, "F29">, DwarfRegNum<[61]>;
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def F30 : Rf<30, "F30">, DwarfRegNum<[62]>;
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def F31 : Rf<31, "F31">, DwarfRegNum<[63]>;
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// Aliases of the F* registers used to hold 64-bit fp values (doubles)
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def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>;
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def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>;
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def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>;
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def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>;
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def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>;
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def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>;
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def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>;
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def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>;
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def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>;
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def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>;
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def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>;
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def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>;
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def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>;
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def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>;
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def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>;
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def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>;
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// Register classes.
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//
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// FIXME: the register order should be defined in terms of the preferred
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// allocation order...
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//
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def IntRegs : RegisterClass<"SP", [i32], 32,
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(add L0, L1, L2, L3, L4, L5, L6,
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L7, I0, I1, I2, I3, I4, I5,
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O0, O1, O2, O3, O4, O5, O7,
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G1,
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// Non-allocatable regs:
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G2, G3, G4, // FIXME: OK for use only in
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// applications, not libraries.
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O6, // stack ptr
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I6, // frame ptr
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I7, // return address
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G0, // constant zero
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G5, G6, G7 // reserved for kernel
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)>;
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def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
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def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>;
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