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https://github.com/c64scene-ar/llvm-6502.git
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0a9481f44f
have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
1.6 KiB
LLVM
70 lines
1.6 KiB
LLVM
; RUN: llc -march=msp430 -combiner-alias-analysis < %s | FileCheck %s
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target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
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target triple = "msp430-generic-generic"
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@foo = common global i16 0, align 2
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@bar = common global i16 0, align 2
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define void @mov() nounwind {
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; CHECK: mov:
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; CHECK: mov.w &bar, &foo
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%1 = load i16* @bar
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store i16 %1, i16* @foo
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ret void
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}
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define void @add() nounwind {
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; CHECK: add:
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; CHECK: add.w &bar, &foo
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%1 = load i16* @bar
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%2 = load i16* @foo
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%3 = add i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define void @and() nounwind {
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; CHECK: and:
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; CHECK: and.w &bar, &foo
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%1 = load i16* @bar
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%2 = load i16* @foo
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%3 = and i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define void @bis() nounwind {
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; CHECK: bis:
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; CHECK: bis.w &bar, &foo
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%1 = load i16* @bar
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%2 = load i16* @foo
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%3 = or i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define void @xor() nounwind {
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; CHECK: xor:
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; CHECK: xor.w &bar, &foo
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%1 = load i16* @bar
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%2 = load i16* @foo
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%3 = xor i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define i16 @mov2() nounwind {
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entry:
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%retval = alloca i16 ; <i16*> [#uses=3]
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%x = alloca i32, align 2 ; <i32*> [#uses=1]
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%y = alloca i32, align 2 ; <i32*> [#uses=1]
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store i16 0, i16* %retval
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%tmp = load i32* %y ; <i32> [#uses=1]
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store i32 %tmp, i32* %x
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store i16 0, i16* %retval
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%0 = load i16* %retval ; <i16> [#uses=1]
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ret i16 %0
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; CHECK: mov2:
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; CHECK: mov.w 0(r1), 4(r1)
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; CHECK: mov.w 2(r1), 6(r1)
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}
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