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https://github.com/c64scene-ar/llvm-6502.git
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b503b49b51
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
191 lines
4.5 KiB
LLVM
191 lines
4.5 KiB
LLVM
; Test 32-bit signed division and remainder.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test register division. The result is in the second of the two registers.
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define void @f1(i32 *%dest, i32 %a, i32 %b) {
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; CHECK: f1:
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; CHECK: lgfr %r1, %r3
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; CHECK: dsgfr %r0, %r4
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; CHECK: st %r1, 0(%r2)
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; CHECK: br %r14
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%div = sdiv i32 %a, %b
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store i32 %div, i32 *%dest
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ret void
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}
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; Test register remainder. The result is in the first of the two registers.
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define void @f2(i32 *%dest, i32 %a, i32 %b) {
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; CHECK: f2:
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; CHECK: lgfr %r1, %r3
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; CHECK: dsgfr %r0, %r4
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; CHECK: st %r0, 0(%r2)
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; CHECK: br %r14
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%rem = srem i32 %a, %b
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store i32 %rem, i32 *%dest
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ret void
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}
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; Test that division and remainder use a single instruction.
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define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
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; CHECK: f3:
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; CHECK-NOT: %r2
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; CHECK: lgfr %r3, %r3
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; CHECK-NOT: %r2
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; CHECK: dsgfr %r2, %r4
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; CHECK-NOT: dsgfr
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Check that the sign extension of the dividend is elided when the argument
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; is already sign-extended.
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define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
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; CHECK: f4:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgfr %r2, %r4
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; CHECK-NOT: dsgfr
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Test that memory dividends are loaded using sign extension (LGF).
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define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f5:
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; CHECK-NOT: %r2
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; CHECK: lgf %r3, 0(%r3)
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; CHECK-NOT: %r2
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; CHECK: dsgfr %r2, %r4
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; CHECK-NOT: dsgfr
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%a = load i32 *%src
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Test memory division with no displacement.
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define void @f6(i32 *%dest, i32 %a, i32 *%src) {
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; CHECK: f6:
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; CHECK: lgfr %r1, %r3
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; CHECK: dsgf %r0, 0(%r4)
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; CHECK: st %r1, 0(%r2)
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; CHECK: br %r14
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%b = load i32 *%src
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%div = sdiv i32 %a, %b
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store i32 %div, i32 *%dest
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ret void
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}
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; Test memory remainder with no displacement.
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define void @f7(i32 *%dest, i32 %a, i32 *%src) {
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; CHECK: f7:
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; CHECK: lgfr %r1, %r3
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; CHECK: dsgf %r0, 0(%r4)
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; CHECK: st %r0, 0(%r2)
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; CHECK: br %r14
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%b = load i32 *%src
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%rem = srem i32 %a, %b
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store i32 %rem, i32 *%dest
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ret void
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}
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; Test both memory division and memory remainder.
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define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK: f8:
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; CHECK-NOT: %r2
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; CHECK: lgfr %r3, %r3
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; CHECK-NOT: %r2
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK-NOT: {{dsgf|dsgfr}}
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%b = load i32 *%src
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Check the high end of the DSGF range.
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define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK: f9:
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; CHECK: dsgf %r2, 524284(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131071
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK: f10:
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; CHECK: agfi %r4, 524288
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131072
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check the high end of the negative aligned DSGF range.
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define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK: f11:
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; CHECK: dsgf %r2, -4(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -1
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check the low end of the DSGF range.
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define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK: f12:
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; CHECK: dsgf %r2, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131072
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK: f13:
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; CHECK: agfi %r4, -524292
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131073
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check that DSGF allows an index.
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define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
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; CHECK: f14:
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; CHECK: dsgf %r2, 524287(%r5,%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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