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https://github.com/c64scene-ar/llvm-6502.git
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475871a144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
488 lines
19 KiB
C++
488 lines
19 KiB
C++
//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAG class, which is used as the common
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// base class for SelectionDAG-based instruction scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SCHEDULEDAG_H
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#define LLVM_CODEGEN_SCHEDULEDAG_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/GraphTraits.h"
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#include "llvm/ADT/SmallSet.h"
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namespace llvm {
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struct InstrStage;
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struct SUnit;
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class MachineConstantPool;
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class MachineFunction;
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class MachineModuleInfo;
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class MachineRegisterInfo;
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class MachineInstr;
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class TargetRegisterInfo;
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class SelectionDAG;
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class SelectionDAGISel;
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class TargetInstrInfo;
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class TargetInstrDesc;
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class TargetLowering;
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class TargetMachine;
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class TargetRegisterClass;
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/// HazardRecognizer - This determines whether or not an instruction can be
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/// issued this cycle, and whether or not a noop needs to be inserted to handle
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/// the hazard.
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class HazardRecognizer {
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public:
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virtual ~HazardRecognizer();
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enum HazardType {
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NoHazard, // This instruction can be emitted at this cycle.
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Hazard, // This instruction can't be emitted at this cycle.
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NoopHazard // This instruction can't be emitted, and needs noops.
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};
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/// getHazardType - Return the hazard type of emitting this node. There are
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/// three possible results. Either:
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/// * NoHazard: it is legal to issue this instruction on this cycle.
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/// * Hazard: issuing this instruction would stall the machine. If some
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/// other instruction is available, issue it first.
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/// * NoopHazard: issuing this instruction would break the program. If
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/// some other instruction can be issued, do so, otherwise issue a noop.
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virtual HazardType getHazardType(SDNode *) {
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return NoHazard;
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}
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/// EmitInstruction - This callback is invoked when an instruction is
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/// emitted, to advance the hazard state.
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virtual void EmitInstruction(SDNode *) {}
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/// AdvanceCycle - This callback is invoked when no instructions can be
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/// issued on this cycle without a hazard. This should increment the
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/// internal state of the hazard recognizer so that previously "Hazard"
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/// instructions will now not be hazards.
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virtual void AdvanceCycle() {}
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/// EmitNoop - This callback is invoked when a noop was added to the
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/// instruction stream.
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virtual void EmitNoop() {}
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};
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/// SDep - Scheduling dependency. It keeps track of dependent nodes,
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/// cost of the depdenency, etc.
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struct SDep {
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SUnit *Dep; // Dependent - either a predecessor or a successor.
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unsigned Reg; // If non-zero, this dep is a phy register dependency.
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int Cost; // Cost of the dependency.
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bool isCtrl : 1; // True iff it's a control dependency.
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bool isSpecial : 1; // True iff it's a special ctrl dep added during sched.
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SDep(SUnit *d, unsigned r, int t, bool c, bool s)
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: Dep(d), Reg(r), Cost(t), isCtrl(c), isSpecial(s) {}
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};
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/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
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/// a group of nodes flagged together.
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struct SUnit {
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SDNode *Node; // Representative node.
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SmallVector<SDNode*,4> FlaggedNodes;// All nodes flagged to Node.
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SUnit *OrigNode; // If not this, the node from which
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// this node was cloned.
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// Preds/Succs - The SUnits before/after us in the graph. The boolean value
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// is true if the edge is a token chain edge, false if it is a value edge.
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SmallVector<SDep, 4> Preds; // All sunit predecessors.
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SmallVector<SDep, 4> Succs; // All sunit successors.
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typedef SmallVector<SDep, 4>::iterator pred_iterator;
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typedef SmallVector<SDep, 4>::iterator succ_iterator;
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typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
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typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
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unsigned NodeNum; // Entry # of node in the node vector.
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unsigned NodeQueueId; // Queue id of node.
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unsigned short Latency; // Node latency.
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short NumPreds; // # of preds.
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short NumSuccs; // # of sucss.
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short NumPredsLeft; // # of preds not scheduled.
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short NumSuccsLeft; // # of succs not scheduled.
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bool isTwoAddress : 1; // Is a two-address instruction.
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bool isCommutable : 1; // Is a commutable instruction.
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bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
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bool isPending : 1; // True once pending.
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bool isAvailable : 1; // True once available.
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bool isScheduled : 1; // True once scheduled.
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unsigned CycleBound; // Upper/lower cycle to be scheduled at.
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unsigned Cycle; // Once scheduled, the cycle of the op.
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unsigned Depth; // Node depth;
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unsigned Height; // Node height;
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const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
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const TargetRegisterClass *CopySrcRC;
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SUnit(SDNode *node, unsigned nodenum)
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: Node(node), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), Latency(0),
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NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
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isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
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isPending(false), isAvailable(false), isScheduled(false),
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CycleBound(0), Cycle(0), Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// addPred - This adds the specified node as a pred of the current node if
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/// not already. This returns true if this is a new pred.
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bool addPred(SUnit *N, bool isCtrl, bool isSpecial,
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unsigned PhyReg = 0, int Cost = 1) {
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for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
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if (Preds[i].Dep == N &&
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Preds[i].isCtrl == isCtrl && Preds[i].isSpecial == isSpecial)
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return false;
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Preds.push_back(SDep(N, PhyReg, Cost, isCtrl, isSpecial));
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N->Succs.push_back(SDep(this, PhyReg, Cost, isCtrl, isSpecial));
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if (!isCtrl) {
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++NumPreds;
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++N->NumSuccs;
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}
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if (!N->isScheduled)
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++NumPredsLeft;
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if (!isScheduled)
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++N->NumSuccsLeft;
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return true;
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}
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bool removePred(SUnit *N, bool isCtrl, bool isSpecial) {
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for (SmallVector<SDep, 4>::iterator I = Preds.begin(), E = Preds.end();
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I != E; ++I)
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if (I->Dep == N && I->isCtrl == isCtrl && I->isSpecial == isSpecial) {
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bool FoundSucc = false;
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for (SmallVector<SDep, 4>::iterator II = N->Succs.begin(),
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EE = N->Succs.end(); II != EE; ++II)
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if (II->Dep == this &&
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II->isCtrl == isCtrl && II->isSpecial == isSpecial) {
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FoundSucc = true;
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N->Succs.erase(II);
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break;
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}
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assert(FoundSucc && "Mismatching preds / succs lists!");
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Preds.erase(I);
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if (!isCtrl) {
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--NumPreds;
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--N->NumSuccs;
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}
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if (!N->isScheduled)
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--NumPredsLeft;
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if (!isScheduled)
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--N->NumSuccsLeft;
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return true;
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}
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return false;
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}
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bool isPred(SUnit *N) {
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for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
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if (Preds[i].Dep == N)
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return true;
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return false;
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}
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bool isSucc(SUnit *N) {
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for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
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if (Succs[i].Dep == N)
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return true;
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return false;
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}
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void dump(const SelectionDAG *G) const;
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void dumpAll(const SelectionDAG *G) const;
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};
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//===--------------------------------------------------------------------===//
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/// SchedulingPriorityQueue - This interface is used to plug different
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/// priorities computation algorithms into the list scheduler. It implements
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/// the interface of a standard priority queue, where nodes are inserted in
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/// arbitrary order and returned in priority order. The computation of the
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/// priority and the representation of the queue are totally up to the
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/// implementation to decide.
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///
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class SchedulingPriorityQueue {
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public:
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virtual ~SchedulingPriorityQueue() {}
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virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
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virtual void addNode(const SUnit *SU) = 0;
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virtual void updateNode(const SUnit *SU) = 0;
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virtual void releaseState() = 0;
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virtual unsigned size() const = 0;
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virtual bool empty() const = 0;
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virtual void push(SUnit *U) = 0;
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virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
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virtual SUnit *pop() = 0;
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virtual void remove(SUnit *SU) = 0;
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/// ScheduledNode - As each node is scheduled, this method is invoked. This
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/// allows the priority function to adjust the priority of related
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/// unscheduled nodes, for example.
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///
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virtual void ScheduledNode(SUnit *) {}
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virtual void UnscheduledNode(SUnit *) {}
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};
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class ScheduleDAG {
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public:
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SelectionDAG &DAG; // DAG of the current basic block
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MachineBasicBlock *BB; // Current basic block
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const TargetMachine &TM; // Target processor
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const TargetInstrInfo *TII; // Target instruction information
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const TargetRegisterInfo *TRI; // Target processor register info
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TargetLowering *TLI; // Target lowering info
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MachineFunction *MF; // Machine function
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MachineRegisterInfo &MRI; // Virtual/real register map
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MachineConstantPool *ConstPool; // Target constant pool
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std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
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// represent noop instructions.
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std::vector<SUnit> SUnits; // The scheduling units.
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SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted.
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ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm);
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virtual ~ScheduleDAG() {}
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/// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
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/// using 'dot'.
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///
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void viewGraph();
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/// Run - perform scheduling.
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///
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void Run();
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/// isPassiveNode - Return true if the node is a non-scheduled leaf.
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///
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static bool isPassiveNode(SDNode *Node) {
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if (isa<ConstantSDNode>(Node)) return true;
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if (isa<ConstantFPSDNode>(Node)) return true;
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if (isa<RegisterSDNode>(Node)) return true;
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if (isa<GlobalAddressSDNode>(Node)) return true;
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if (isa<BasicBlockSDNode>(Node)) return true;
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if (isa<FrameIndexSDNode>(Node)) return true;
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if (isa<ConstantPoolSDNode>(Node)) return true;
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if (isa<JumpTableSDNode>(Node)) return true;
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if (isa<ExternalSymbolSDNode>(Node)) return true;
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if (isa<MemOperandSDNode>(Node)) return true;
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if (Node->getOpcode() == ISD::EntryToken) return true;
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return false;
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}
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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///
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SUnit *NewSUnit(SDNode *N) {
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SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
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SUnits.back().OrigNode = &SUnits.back();
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return &SUnits.back();
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}
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/// Clone - Creates a clone of the specified SUnit. It does not copy the
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/// predecessors / successors info nor the temporary scheduling states.
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SUnit *Clone(SUnit *N);
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/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
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/// This SUnit graph is similar to the SelectionDAG, but represents flagged
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/// together nodes with a single SUnit.
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void BuildSchedUnits();
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/// ComputeLatency - Compute node latency.
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///
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void ComputeLatency(SUnit *SU);
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/// CalculateDepths, CalculateHeights - Calculate node depth / height.
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///
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void CalculateDepths();
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void CalculateHeights();
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands
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/// (which do not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node);
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// followed by special operands that describe memory references, then an
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/// optional chain operand, then flag operands. Compute the number of
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/// actual operands that will go into the resulting MachineInstr.
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static unsigned CountOperands(SDNode *Node);
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/// ComputeMemOperandsEnd - Find the index one past the last
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/// MemOperandSDNode operand
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static unsigned ComputeMemOperandsEnd(SDNode *Node);
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/// EmitNode - Generate machine code for an node and needed dependencies.
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/// VRBaseMap contains, for each already emitted node, the first virtual
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/// register number for the results of the node.
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///
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void EmitNode(SDNode *Node, bool IsClone,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// EmitNoop - Emit a noop instruction.
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///
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void EmitNoop();
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MachineBasicBlock *EmitSchedule();
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void dumpSchedule() const;
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/// Schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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///
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virtual void Schedule() = 0;
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private:
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/// EmitSubregNode - Generate machine code for subreg nodes.
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///
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void EmitSubregNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
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/// getDstOfCopyToRegUse - If the only use of the specified result number of
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/// node is a CopyToReg, return its destination register. Return 0 otherwise.
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unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
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void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
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void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
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unsigned SrcReg,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
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/// physical register has only a single copy use, then coalesced the copy
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/// if possible.
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void EmitLiveInCopy(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &InsertPos,
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unsigned VirtReg, unsigned PhysReg,
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const TargetRegisterClass *RC,
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DenseMap<MachineInstr*, unsigned> &CopyRegMap);
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/// EmitLiveInCopies - If this is the first basic block in the function,
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/// and if it has live ins that need to be copied into vregs, emit the
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/// copies into the top of the block.
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void EmitLiveInCopies(MachineBasicBlock *MBB);
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};
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/// createBURRListDAGScheduler - This creates a bottom up register usage
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/// reduction list scheduler.
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ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB,
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bool Fast);
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/// createTDRRListDAGScheduler - This creates a top down register usage
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/// reduction list scheduler.
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ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB,
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bool Fast);
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/// createTDListDAGScheduler - This creates a top-down list scheduler with
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/// a hazard recognizer.
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ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB,
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bool Fast);
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/// createDefaultScheduler - This creates an instruction scheduler appropriate
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/// for the target.
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ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB,
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bool Fast);
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class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> {
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SUnit *Node;
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unsigned Operand;
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SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
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public:
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bool operator==(const SUnitIterator& x) const {
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return Operand == x.Operand;
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}
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bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
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const SUnitIterator &operator=(const SUnitIterator &I) {
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assert(I.Node == Node && "Cannot assign iterators to two different nodes!");
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Operand = I.Operand;
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return *this;
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}
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pointer operator*() const {
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return Node->Preds[Operand].Dep;
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}
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pointer operator->() const { return operator*(); }
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SUnitIterator& operator++() { // Preincrement
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++Operand;
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return *this;
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}
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SUnitIterator operator++(int) { // Postincrement
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SUnitIterator tmp = *this; ++*this; return tmp;
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}
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static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
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static SUnitIterator end (SUnit *N) {
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return SUnitIterator(N, (unsigned)N->Preds.size());
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}
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unsigned getOperand() const { return Operand; }
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const SUnit *getNode() const { return Node; }
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bool isCtrlDep() const { return Node->Preds[Operand].isCtrl; }
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bool isSpecialDep() const { return Node->Preds[Operand].isSpecial; }
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};
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template <> struct GraphTraits<SUnit*> {
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typedef SUnit NodeType;
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typedef SUnitIterator ChildIteratorType;
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static inline NodeType *getEntryNode(SUnit *N) { return N; }
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static inline ChildIteratorType child_begin(NodeType *N) {
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return SUnitIterator::begin(N);
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}
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static inline ChildIteratorType child_end(NodeType *N) {
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return SUnitIterator::end(N);
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}
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};
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template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
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typedef std::vector<SUnit>::iterator nodes_iterator;
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static nodes_iterator nodes_begin(ScheduleDAG *G) {
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|
return G->SUnits.begin();
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|
}
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|
static nodes_iterator nodes_end(ScheduleDAG *G) {
|
|
return G->SUnits.end();
|
|
}
|
|
};
|
|
}
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|
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#endif
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