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This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126259 91177308-0d34-0410-b5e6-96231b3b80d8
538 lines
19 KiB
C++
538 lines
19 KiB
C++
//===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RABasic function pass, which provides a minimal
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// implementation of the basic register allocator.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "LiveIntervalUnion.h"
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#include "RegAllocBase.h"
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#include "RenderMachineFunction.h"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Function.h"
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#include "llvm/PassAnalysisSupport.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#ifndef NDEBUG
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#include "llvm/ADT/SparseBitVector.h"
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#endif
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Timer.h"
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#include <cstdlib>
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#include <queue>
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using namespace llvm;
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STATISTIC(NumAssigned , "Number of registers assigned");
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STATISTIC(NumUnassigned , "Number of registers unassigned");
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STATISTIC(NumNewQueued , "Number of new live ranges queued");
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static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
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createBasicRegisterAllocator);
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// Temporary verification option until we can put verification inside
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// MachineVerifier.
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static cl::opt<bool, true>
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VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
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cl::desc("Verify during register allocation"));
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const char *RegAllocBase::TimerGroupName = "Register Allocation";
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bool RegAllocBase::VerifyEnabled = false;
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namespace {
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struct CompSpillWeight {
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bool operator()(LiveInterval *A, LiveInterval *B) const {
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return A->weight < B->weight;
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}
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};
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}
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namespace {
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/// RABasic provides a minimal implementation of the basic register allocation
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/// algorithm. It prioritizes live virtual registers by spill weight and spills
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/// whenever a register is unavailable. This is not practical in production but
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/// provides a useful baseline both for measuring other allocators and comparing
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/// the speed of the basic algorithm against other styles of allocators.
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class RABasic : public MachineFunctionPass, public RegAllocBase
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{
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// context
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MachineFunction *MF;
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BitVector ReservedRegs;
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// analyses
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LiveStacks *LS;
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RenderMachineFunction *RMF;
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// state
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std::auto_ptr<Spiller> SpillerInstance;
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std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
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CompSpillWeight> Queue;
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public:
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RABasic();
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/// Return the pass name.
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virtual const char* getPassName() const {
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return "Basic Register Allocator";
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}
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/// RABasic analysis usage.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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virtual Spiller &spiller() { return *SpillerInstance; }
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virtual float getPriority(LiveInterval *LI) { return LI->weight; }
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virtual void enqueue(LiveInterval *LI) {
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Queue.push(LI);
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}
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virtual LiveInterval *dequeue() {
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if (Queue.empty())
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return 0;
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LiveInterval *LI = Queue.top();
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Queue.pop();
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return LI;
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}
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virtual unsigned selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs);
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/// Perform register allocation.
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virtual bool runOnMachineFunction(MachineFunction &mf);
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static char ID;
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};
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char RABasic::ID = 0;
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} // end anonymous namespace
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RABasic::RABasic(): MachineFunctionPass(ID) {
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
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initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
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initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
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initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
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initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
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initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
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initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
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initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
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}
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void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<AliasAnalysis>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<SlotIndexes>();
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if (StrongPHIElim)
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AU.addRequiredID(StrongPHIEliminationID);
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AU.addRequiredTransitive<RegisterCoalescer>();
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AU.addRequired<CalculateSpillWeights>();
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AU.addRequired<LiveStacks>();
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AU.addPreserved<LiveStacks>();
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AU.addRequiredID(MachineDominatorsID);
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AU.addPreservedID(MachineDominatorsID);
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addRequired<VirtRegMap>();
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AU.addPreserved<VirtRegMap>();
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DEBUG(AU.addRequired<RenderMachineFunction>());
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void RABasic::releaseMemory() {
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SpillerInstance.reset(0);
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RegAllocBase::releaseMemory();
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}
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#ifndef NDEBUG
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// Verify each LiveIntervalUnion.
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void RegAllocBase::verify() {
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LiveVirtRegBitSet VisitedVRegs;
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OwningArrayPtr<LiveVirtRegBitSet>
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unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
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// Verify disjoint unions.
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for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
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DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
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LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
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PhysReg2LiveUnion[PhysReg].verify(VRegs);
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// Union + intersection test could be done efficiently in one pass, but
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// don't add a method to SparseBitVector unless we really need it.
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assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
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VisitedVRegs |= VRegs;
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}
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// Verify vreg coverage.
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for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
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liItr != liEnd; ++liItr) {
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unsigned reg = liItr->first;
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if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
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if (!VRM->hasPhys(reg)) continue; // spilled?
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unsigned PhysReg = VRM->getPhys(reg);
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if (!unionVRegs[PhysReg].test(reg)) {
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dbgs() << "LiveVirtReg " << reg << " not in union " <<
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TRI->getName(PhysReg) << "\n";
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llvm_unreachable("unallocated live vreg");
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}
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}
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// FIXME: I'm not sure how to verify spilled intervals.
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}
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#endif //!NDEBUG
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//===----------------------------------------------------------------------===//
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// RegAllocBase Implementation
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//===----------------------------------------------------------------------===//
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// Instantiate a LiveIntervalUnion for each physical register.
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void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
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unsigned NRegs) {
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NumRegs = NRegs;
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Array =
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static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
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for (unsigned r = 0; r != NRegs; ++r)
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new(Array + r) LiveIntervalUnion(r, allocator);
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}
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void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
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NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
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TRI = &vrm.getTargetRegInfo();
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MRI = &vrm.getRegInfo();
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VRM = &vrm;
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LIS = &lis;
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PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
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// Cache an interferece query for each physical reg
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Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
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}
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void RegAllocBase::LiveUnionArray::clear() {
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if (!Array)
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return;
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for (unsigned r = 0; r != NumRegs; ++r)
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Array[r].~LiveIntervalUnion();
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free(Array);
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NumRegs = 0;
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Array = 0;
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}
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void RegAllocBase::releaseMemory() {
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PhysReg2LiveUnion.clear();
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}
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// Visit all the live registers. If they are already assigned to a physical
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// register, unify them with the corresponding LiveIntervalUnion, otherwise push
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// them on the priority queue for later assignment.
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void RegAllocBase::seedLiveRegs() {
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for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
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unsigned RegNum = I->first;
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LiveInterval &VirtReg = *I->second;
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if (TargetRegisterInfo::isPhysicalRegister(RegNum))
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PhysReg2LiveUnion[RegNum].unify(VirtReg);
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else
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enqueue(&VirtReg);
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}
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}
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void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
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DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
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<< " to " << PrintReg(PhysReg, TRI) << '\n');
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assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
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VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
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PhysReg2LiveUnion[PhysReg].unify(VirtReg);
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++NumAssigned;
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}
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void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
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DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
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<< " from " << PrintReg(PhysReg, TRI) << '\n');
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assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
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PhysReg2LiveUnion[PhysReg].extract(VirtReg);
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VRM->clearVirt(VirtReg.reg);
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++NumUnassigned;
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}
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// Top-level driver to manage the queue of unassigned VirtRegs and call the
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// selectOrSplit implementation.
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void RegAllocBase::allocatePhysRegs() {
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seedLiveRegs();
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// Continue assigning vregs one at a time to available physical registers.
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while (LiveInterval *VirtReg = dequeue()) {
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// selectOrSplit requests the allocator to return an available physical
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// register if possible and populate a list of new live intervals that
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// result from splitting.
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DEBUG(dbgs() << "\nselectOrSplit "
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<< MRI->getRegClass(VirtReg->reg)->getName()
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<< ':' << *VirtReg << '\n');
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typedef SmallVector<LiveInterval*, 4> VirtRegVec;
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VirtRegVec SplitVRegs;
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unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
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if (AvailablePhysReg)
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assign(*VirtReg, AvailablePhysReg);
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for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
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I != E; ++I) {
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LiveInterval *SplitVirtReg = *I;
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if (SplitVirtReg->empty()) continue;
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DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
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assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
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"expect split value in virtual register");
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enqueue(SplitVirtReg);
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++NumNewQueued;
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}
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}
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}
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// Check if this live virtual register interferes with a physical register. If
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// not, then check for interference on each register that aliases with the
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// physical register. Return the interfering register.
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unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
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unsigned PhysReg) {
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for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
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if (query(VirtReg, *AliasI).checkInterference())
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return *AliasI;
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return 0;
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}
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// Helper for spillInteferences() that spills all interfering vregs currently
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// assigned to this physical register.
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void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs) {
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LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
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assert(Q.seenAllInterferences() && "need collectInterferences()");
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const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
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for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
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E = PendingSpills.end(); I != E; ++I) {
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LiveInterval &SpilledVReg = **I;
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DEBUG(dbgs() << "extracting from " <<
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TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
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// Deallocate the interfering vreg by removing it from the union.
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// A LiveInterval instance may not be in a union during modification!
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unassign(SpilledVReg, PhysReg);
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// Spill the extracted interval.
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spiller().spill(&SpilledVReg, SplitVRegs, PendingSpills);
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}
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// After extracting segments, the query's results are invalid. But keep the
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// contents valid until we're done accessing pendingSpills.
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Q.clear();
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}
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// Spill or split all live virtual registers currently unified under PhysReg
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// that interfere with VirtReg. The newly spilled or split live intervals are
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// returned by appending them to SplitVRegs.
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bool
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RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs) {
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// Record each interference and determine if all are spillable before mutating
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// either the union or live intervals.
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unsigned NumInterferences = 0;
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// Collect interferences assigned to any alias of the physical register.
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for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
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LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
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NumInterferences += QAlias.collectInterferingVRegs();
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if (QAlias.seenUnspillableVReg()) {
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return false;
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}
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}
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DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
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" interferences with " << VirtReg << "\n");
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assert(NumInterferences > 0 && "expect interference");
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// Spill each interfering vreg allocated to PhysReg or an alias.
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for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
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spillReg(VirtReg, *AliasI, SplitVRegs);
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return true;
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}
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// Add newly allocated physical registers to the MBB live in sets.
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void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
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NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
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typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
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MBBVec liveInMBBs;
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MachineBasicBlock &entryMBB = *MF->begin();
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for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
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LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
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if (LiveUnion.empty())
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continue;
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for (LiveIntervalUnion::SegmentIter SI = LiveUnion.begin(); SI.valid();
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++SI) {
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// Find the set of basic blocks which this range is live into...
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liveInMBBs.clear();
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if (!LIS->findLiveInMBBs(SI.start(), SI.stop(), liveInMBBs)) continue;
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// And add the physreg for this interval to their live-in sets.
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for (MBBVec::iterator I = liveInMBBs.begin(), E = liveInMBBs.end();
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I != E; ++I) {
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MachineBasicBlock *MBB = *I;
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if (MBB == &entryMBB) continue;
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if (MBB->isLiveIn(PhysReg)) continue;
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MBB->addLiveIn(PhysReg);
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}
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// RABasic Implementation
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//===----------------------------------------------------------------------===//
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// Driver for the register assignment and splitting heuristics.
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// Manages iteration over the LiveIntervalUnions.
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//
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// This is a minimal implementation of register assignment and splitting that
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// spills whenever we run out of registers.
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//
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// selectOrSplit can only be called once per live virtual register. We then do a
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// single interference test for each register the correct class until we find an
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// available register. So, the number of interference tests in the worst case is
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// |vregs| * |machineregs|. And since the number of interference tests is
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// minimal, there is no value in caching them outside the scope of
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// selectOrSplit().
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unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs) {
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// Populate a list of physical register spill candidates.
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SmallVector<unsigned, 8> PhysRegSpillCands;
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// Check for an available register in this class.
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const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
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for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
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E = TRC->allocation_order_end(*MF);
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I != E; ++I) {
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unsigned PhysReg = *I;
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if (ReservedRegs.test(PhysReg)) continue;
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// Check interference and as a side effect, intialize queries for this
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// VirtReg and its aliases.
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unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
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if (interfReg == 0) {
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// Found an available register.
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return PhysReg;
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}
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LiveInterval *interferingVirtReg =
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Queries[interfReg].firstInterference().liveUnionPos().value();
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// The current VirtReg must either be spillable, or one of its interferences
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// must have less spill weight.
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if (interferingVirtReg->weight < VirtReg.weight ) {
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PhysRegSpillCands.push_back(PhysReg);
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}
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}
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// Try to spill another interfering reg with less spill weight.
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for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
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PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
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if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
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assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
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"Interference after spill.");
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// Tell the caller to allocate to this newly freed physical register.
|
|
return *PhysRegI;
|
|
}
|
|
// No other spill candidates were found, so spill the current VirtReg.
|
|
DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
|
|
SmallVector<LiveInterval*, 1> pendingSpills;
|
|
|
|
spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
|
|
|
|
// The live virtual register requesting allocation was spilled, so tell
|
|
// the caller not to allocate anything during this round.
|
|
return 0;
|
|
}
|
|
|
|
bool RABasic::runOnMachineFunction(MachineFunction &mf) {
|
|
DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
|
|
<< "********** Function: "
|
|
<< ((Value*)mf.getFunction())->getName() << '\n');
|
|
|
|
MF = &mf;
|
|
DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
|
|
|
|
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
|
|
|
|
ReservedRegs = TRI->getReservedRegs(*MF);
|
|
|
|
SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
|
|
|
|
allocatePhysRegs();
|
|
|
|
addMBBLiveIns(MF);
|
|
|
|
// Diagnostic output before rewriting
|
|
DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
|
|
|
|
// optional HTML output
|
|
DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
|
|
|
|
// FIXME: Verification currently must run before VirtRegRewriter. We should
|
|
// make the rewriter a separate pass and override verifyAnalysis instead. When
|
|
// that happens, verification naturally falls under VerifyMachineCode.
|
|
#ifndef NDEBUG
|
|
if (VerifyEnabled) {
|
|
// Verify accuracy of LiveIntervals. The standard machine code verifier
|
|
// ensures that each LiveIntervals covers all uses of the virtual reg.
|
|
|
|
// FIXME: MachineVerifier is badly broken when using the standard
|
|
// spiller. Always use -spiller=inline with -verify-regalloc. Even with the
|
|
// inline spiller, some tests fail to verify because the coalescer does not
|
|
// always generate verifiable code.
|
|
MF->verify(this, "In RABasic::verify");
|
|
|
|
// Verify that LiveIntervals are partitioned into unions and disjoint within
|
|
// the unions.
|
|
verify();
|
|
}
|
|
#endif // !NDEBUG
|
|
|
|
// Run rewriter
|
|
VRM->rewrite(LIS->getSlotIndexes());
|
|
|
|
// The pass output is in VirtRegMap. Release all the transient data.
|
|
releaseMemory();
|
|
|
|
return true;
|
|
}
|
|
|
|
FunctionPass* llvm::createBasicRegisterAllocator()
|
|
{
|
|
return new RABasic();
|
|
}
|