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c589d1b3bc
Implement CACHE and PREF instructions using mapping. Differential Revision: http://reviews.llvm.org/D8893 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235379 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
1.1 KiB
TableGen
45 lines
1.1 KiB
TableGen
//=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes microMIPS32r6 instruction formats.
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//
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//===----------------------------------------------------------------------===//
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class MMR6Arch<string opstr> {
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string Arch = "micromipsr6";
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string BaseOpcode = opstr;
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}
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class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rd;
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let Inst{15-12} = 0b0000;
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let Inst{11-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
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bits<21> addr;
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bits<5> hint;
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bits<32> Inst;
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let Inst{31-26} = opgroup;
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let Inst{25-21} = hint;
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let Inst{20-16} = addr{20-16};
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let Inst{15-12} = funct;
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let Inst{11-0} = addr{11-0};
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}
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