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a6f7499244
Add an extra run with -regalloc=basic to keep them honest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.0 KiB
LLVM
54 lines
1.0 KiB
LLVM
; RUN: llc < %s -march=xcore | FileCheck %s
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; RUN: llc < %s -march=xcore -regalloc=basic | FileCheck %s
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define i64 @umul_lohi(i32 %a, i32 %b) {
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entry:
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%0 = zext i32 %a to i64
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%1 = zext i32 %b to i64
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%2 = mul i64 %1, %0
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ret i64 %2
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}
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; CHECK: umul_lohi:
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; CHECK: ldc [[REG:r[0-9]+]], 0
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; CHECK-NEXT: lmul r1, r0, r1, r0, [[REG]], [[REG]]
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; CHECK-NEXT: retsp 0
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define i64 @smul_lohi(i32 %a, i32 %b) {
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entry:
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%0 = sext i32 %a to i64
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%1 = sext i32 %b to i64
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%2 = mul i64 %1, %0
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ret i64 %2
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}
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; CHECK: smul_lohi:
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; CHECK: ldc
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; CHECK-NEXT: mov
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; CHECK-NEXT: maccs
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; CHECK-NEXT: mov r0,
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; CHECK-NEXT: mov r1,
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; CHECK-NEXT: retsp 0
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define i64 @mul64(i64 %a, i64 %b) {
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entry:
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%0 = mul i64 %a, %b
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ret i64 %0
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}
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; CHECK: mul64:
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; CHECK: ldc
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; CHECK-NEXT: lmul
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; CHECK-NEXT: mul
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; CHECK-NEXT: lmul
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; CHECK-NEXT: mov r0,
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define i64 @mul64_2(i64 %a, i32 %b) {
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entry:
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%0 = zext i32 %b to i64
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%1 = mul i64 %a, %0
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ret i64 %1
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}
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; CHECK: mul64_2:
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; CHECK: ldc
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; CHECK-NEXT: lmul
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; CHECK-NEXT: mul
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; CHECK-NEXT: add r1,
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; CHECK-NEXT: retsp 0
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