llvm-6502/test/CodeGen/X86/dagcombine_unsafe_math.ll
Shuxin Yang 1cd1d02141 Disable some unsafe-fp-math DAG-combine transformation after legalization.
For instance, following transformation will be disabled:
    x + x + x => 3.0f * x;

The problem of these transformations is that it introduces a FP constant, which
following Instruction-Selection pass cannot handle.

Reviewed by Nadav, thanks a lot!

rdar://13445387


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177933 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 22:52:29 +00:00

57 lines
1.5 KiB
LLVM

; RUN: llc < %s -enable-unsafe-fp-math -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s
; rdar://13126763
; Expression "x + x*x" was mistakenly transformed into "x * 3.0f".
define float @test1(float %x) {
%t1 = fmul fast float %x, %x
%t2 = fadd fast float %t1, %x
ret float %t2
; CHECK: test1
; CHECK: vaddss
}
; (x + x) + x => x * 3.0
define float @test2(float %x) {
%t1 = fadd fast float %x, %x
%t2 = fadd fast float %t1, %x
ret float %t2
; CHECK: .long 1077936128
; CHECK: test2
; CHECK: vmulss LCPI1_0(%rip), %xmm0, %xmm0
}
; x + (x + x) => x * 3.0
define float @test3(float %x) {
%t1 = fadd fast float %x, %x
%t2 = fadd fast float %t1, %x
ret float %t2
; CHECK: .long 1077936128
; CHECK: test3
; CHECK: vmulss LCPI2_0(%rip), %xmm0, %xmm0
}
; (y + x) + x != x * 3.0
define float @test4(float %x, float %y) {
%t1 = fadd fast float %x, %y
%t2 = fadd fast float %t1, %x
ret float %t2
; CHECK: test4
; CHECK: vaddss
}
; rdar://13445387
; "x + x + x => 3.0 * x" should be disabled after legalization because
; Instruction-Selection dosen't know how to handle "3.0"
;
define float @test5() {
%mul.i.i151 = fmul <4 x float> zeroinitializer, zeroinitializer
%vecext.i8.i152 = extractelement <4 x float> %mul.i.i151, i32 1
%vecext1.i9.i153 = extractelement <4 x float> %mul.i.i151, i32 0
%add.i10.i154 = fadd float %vecext1.i9.i153, %vecext.i8.i152
%vecext.i7.i155 = extractelement <4 x float> %mul.i.i151, i32 2
%add.i.i156 = fadd float %vecext.i7.i155, %add.i10.i154
ret float %add.i.i156
}