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d9df501704
register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
1.1 KiB
C++
38 lines
1.1 KiB
C++
//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Constant.h"
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#include "llvm/DerivedTypes.h"
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using namespace llvm;
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TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
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unsigned numOpcodes)
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: Descriptors(Desc), NumOpcodes(numOpcodes) {
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}
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TargetInstrInfo::~TargetInstrInfo() {
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}
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bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isTerminator()) return false;
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// Conditional branch is a special case.
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if (TID.isBranch() && !TID.isBarrier())
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return true;
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if (!TID.isPredicable())
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return true;
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return !isPredicated(MI);
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}
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