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DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
695 lines
24 KiB
C++
695 lines
24 KiB
C++
//===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a top-down list scheduler, using standard algorithms.
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// The basic approach uses a priority queue of available nodes to schedule.
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// One at a time, nodes are taken from the priority queue (thus in priority
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// order), checked for legality to schedule, and emitted if legal.
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//
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// Nodes may not be legal to schedule either due to structural hazards (e.g.
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// pipeline or resource constraints) or because an input to the instruction has
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// not completed execution.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "post-RA-sched"
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#include "AntiDepBreaker.h"
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#include "AggressiveAntiDepBreaker.h"
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#include "CriticalAntiDepBreaker.h"
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#include "ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtarget.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/Statistic.h"
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#include <set>
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using namespace llvm;
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STATISTIC(NumNoops, "Number of noops inserted");
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STATISTIC(NumStalls, "Number of pipeline stalls");
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STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
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// Post-RA scheduling is enabled with
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// TargetSubtarget.enablePostRAScheduler(). This flag can be used to
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// override the target.
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static cl::opt<bool>
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EnablePostRAScheduler("post-RA-scheduler",
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cl::desc("Enable scheduling after register allocation"),
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cl::init(false), cl::Hidden);
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static cl::opt<std::string>
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EnableAntiDepBreaking("break-anti-dependencies",
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cl::desc("Break post-RA scheduling anti-dependencies: "
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"\"critical\", \"all\", or \"none\""),
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cl::init("none"), cl::Hidden);
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// If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
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static cl::opt<int>
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DebugDiv("postra-sched-debugdiv",
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cl::desc("Debug control MBBs that are scheduled"),
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cl::init(0), cl::Hidden);
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static cl::opt<int>
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DebugMod("postra-sched-debugmod",
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cl::desc("Debug control MBBs that are scheduled"),
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cl::init(0), cl::Hidden);
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AntiDepBreaker::~AntiDepBreaker() { }
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namespace {
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class PostRAScheduler : public MachineFunctionPass {
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AliasAnalysis *AA;
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const TargetInstrInfo *TII;
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CodeGenOpt::Level OptLevel;
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public:
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static char ID;
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PostRAScheduler(CodeGenOpt::Level ol) :
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MachineFunctionPass(ID), OptLevel(ol) {}
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const char *getPassName() const {
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return "Post RA top-down list latency scheduler";
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}
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bool runOnMachineFunction(MachineFunction &Fn);
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};
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char PostRAScheduler::ID = 0;
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class SchedulePostRATDList : public ScheduleDAGInstrs {
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/// AvailableQueue - The priority queue to use for the available SUnits.
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///
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LatencyPriorityQueue AvailableQueue;
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/// PendingQueue - This contains all of the instructions whose operands have
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/// been issued, but their results are not ready yet (due to the latency of
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/// the operation). Once the operands becomes available, the instruction is
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/// added to the AvailableQueue.
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std::vector<SUnit*> PendingQueue;
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/// Topo - A topological ordering for SUnits.
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ScheduleDAGTopologicalSort Topo;
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/// HazardRec - The hazard recognizer to use.
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ScheduleHazardRecognizer *HazardRec;
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/// AntiDepBreak - Anti-dependence breaking object, or NULL if none
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AntiDepBreaker *AntiDepBreak;
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/// AA - AliasAnalysis for making memory reference queries.
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AliasAnalysis *AA;
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/// KillIndices - The index of the most recent kill (proceding bottom-up),
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/// or ~0u if the register is not live.
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std::vector<unsigned> KillIndices;
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public:
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SchedulePostRATDList(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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AliasAnalysis *AA, TargetSubtarget::AntiDepBreakMode AntiDepMode,
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SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs);
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~SchedulePostRATDList();
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/// StartBlock - Initialize register live-range state for scheduling in
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/// this block.
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///
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void StartBlock(MachineBasicBlock *BB);
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/// Schedule - Schedule the instruction range using list scheduling.
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///
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void Schedule();
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/// Observe - Update liveness information to account for the current
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/// instruction, which will not be scheduled.
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///
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void Observe(MachineInstr *MI, unsigned Count);
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/// FinishBlock - Clean up register live-range state.
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///
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void FinishBlock();
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/// FixupKills - Fix register kill flags that have been made
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/// invalid due to scheduling
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///
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void FixupKills(MachineBasicBlock *MBB);
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private:
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void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
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void ReleaseSuccessors(SUnit *SU);
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void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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void ListScheduleTopDown();
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void StartBlockForKills(MachineBasicBlock *BB);
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// ToggleKillFlag - Toggle a register operand kill flag. Other
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// adjustments may be made to the instruction if necessary. Return
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// true if the operand has been deleted, false if not.
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bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
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};
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}
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SchedulePostRATDList::SchedulePostRATDList(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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AliasAnalysis *AA, TargetSubtarget::AntiDepBreakMode AntiDepMode,
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SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs)
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: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits), AA(AA),
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KillIndices(TRI->getNumRegs())
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{
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const TargetMachine &TM = MF.getTarget();
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const InstrItineraryData *InstrItins = TM.getInstrItineraryData();
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HazardRec =
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TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
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AntiDepBreak =
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((AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ?
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(AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, CriticalPathRCs) :
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((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
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(AntiDepBreaker *)new CriticalAntiDepBreaker(MF) : NULL));
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}
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SchedulePostRATDList::~SchedulePostRATDList() {
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delete HazardRec;
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delete AntiDepBreak;
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}
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bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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TII = Fn.getTarget().getInstrInfo();
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MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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AliasAnalysis *AA = &getAnalysis<AliasAnalysis>();
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// Check for explicit enable/disable of post-ra scheduling.
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TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE;
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SmallVector<TargetRegisterClass*, 4> CriticalPathRCs;
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if (EnablePostRAScheduler.getPosition() > 0) {
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if (!EnablePostRAScheduler)
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return false;
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} else {
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// Check that post-RA scheduling is enabled for this target.
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// This may upgrade the AntiDepMode.
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const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
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if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode, CriticalPathRCs))
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return false;
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}
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// Check for antidep breaking override...
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if (EnableAntiDepBreaking.getPosition() > 0) {
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AntiDepMode = (EnableAntiDepBreaking == "all") ?
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TargetSubtarget::ANTIDEP_ALL :
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(EnableAntiDepBreaking == "critical")
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? TargetSubtarget::ANTIDEP_CRITICAL : TargetSubtarget::ANTIDEP_NONE;
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}
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DEBUG(dbgs() << "PostRAScheduler\n");
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SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, AntiDepMode,
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CriticalPathRCs);
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// Loop over all of the basic blocks
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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#ifndef NDEBUG
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// If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
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if (DebugDiv > 0) {
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static int bbcnt = 0;
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if (bbcnt++ % DebugDiv != DebugMod)
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continue;
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dbgs() << "*** DEBUG scheduling " << Fn.getFunction()->getNameStr() <<
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":BB#" << MBB->getNumber() << " ***\n";
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}
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#endif
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// Initialize register live-range state for scheduling in this block.
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Scheduler.StartBlock(MBB);
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// Schedule each sequence of instructions not interrupted by a label
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// or anything else that effectively needs to shut down scheduling.
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MachineBasicBlock::iterator Current = MBB->end();
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unsigned Count = MBB->size(), CurrentCount = Count;
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for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
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MachineInstr *MI = llvm::prior(I);
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if (TII->isSchedulingBoundary(MI, MBB, Fn)) {
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Scheduler.Run(MBB, I, Current, CurrentCount);
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Scheduler.EmitSchedule();
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Current = MI;
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CurrentCount = Count - 1;
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Scheduler.Observe(MI, CurrentCount);
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}
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I = MI;
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--Count;
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}
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assert(Count == 0 && "Instruction count mismatch!");
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assert((MBB->begin() == Current || CurrentCount != 0) &&
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"Instruction count mismatch!");
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Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
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Scheduler.EmitSchedule();
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// Clean up register live-range state.
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Scheduler.FinishBlock();
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// Update register kills
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Scheduler.FixupKills(MBB);
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}
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return true;
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}
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/// StartBlock - Initialize register live-range state for scheduling in
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/// this block.
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///
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void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
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// Call the superclass.
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ScheduleDAGInstrs::StartBlock(BB);
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// Reset the hazard recognizer and anti-dep breaker.
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HazardRec->Reset();
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if (AntiDepBreak != NULL)
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AntiDepBreak->StartBlock(BB);
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}
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/// Schedule - Schedule the instruction range using list scheduling.
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///
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void SchedulePostRATDList::Schedule() {
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// Build the scheduling graph.
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BuildSchedGraph(AA);
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if (AntiDepBreak != NULL) {
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unsigned Broken =
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AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos,
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InsertPosIndex);
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if (Broken != 0) {
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// We made changes. Update the dependency graph.
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// Theoretically we could update the graph in place:
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// When a live range is changed to use a different register, remove
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// the def's anti-dependence *and* output-dependence edges due to
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// that register, and add new anti-dependence and output-dependence
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// edges based on the next live range of the register.
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SUnits.clear();
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Sequence.clear();
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EntrySU = SUnit();
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ExitSU = SUnit();
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BuildSchedGraph(AA);
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NumFixedAnti += Broken;
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}
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}
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DEBUG(dbgs() << "********** List Scheduling **********\n");
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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AvailableQueue.initNodes(SUnits);
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ListScheduleTopDown();
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AvailableQueue.releaseState();
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}
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/// Observe - Update liveness information to account for the current
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/// instruction, which will not be scheduled.
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///
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void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
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if (AntiDepBreak != NULL)
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AntiDepBreak->Observe(MI, Count, InsertPosIndex);
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}
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/// FinishBlock - Clean up register live-range state.
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///
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void SchedulePostRATDList::FinishBlock() {
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if (AntiDepBreak != NULL)
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AntiDepBreak->FinishBlock();
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// Call the superclass.
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ScheduleDAGInstrs::FinishBlock();
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}
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/// StartBlockForKills - Initialize register live-range state for updating kills
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///
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void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
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// Initialize the indices to indicate that no registers are live.
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for (unsigned i = 0; i < TRI->getNumRegs(); ++i)
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KillIndices[i] = ~0u;
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// Determine the live-out physregs for this block.
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if (!BB->empty() && BB->back().getDesc().isReturn()) {
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// In a return block, examine the function live-out regs.
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for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
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E = MRI.liveout_end(); I != E; ++I) {
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unsigned Reg = *I;
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KillIndices[Reg] = BB->size();
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// Repeat, for all subregs.
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg) {
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KillIndices[*Subreg] = BB->size();
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}
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}
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}
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else {
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// In a non-return block, examine the live-in regs of all successors.
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI) {
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for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
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E = (*SI)->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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KillIndices[Reg] = BB->size();
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// Repeat, for all subregs.
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg) {
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KillIndices[*Subreg] = BB->size();
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}
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}
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}
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}
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}
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bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
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MachineOperand &MO) {
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// Setting kill flag...
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if (!MO.isKill()) {
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MO.setIsKill(true);
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return false;
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}
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// If MO itself is live, clear the kill flag...
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if (KillIndices[MO.getReg()] != ~0u) {
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MO.setIsKill(false);
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return false;
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}
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// If any subreg of MO is live, then create an imp-def for that
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// subreg and keep MO marked as killed.
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MO.setIsKill(false);
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bool AllDead = true;
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const unsigned SuperReg = MO.getReg();
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for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg);
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*Subreg; ++Subreg) {
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if (KillIndices[*Subreg] != ~0u) {
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MI->addOperand(MachineOperand::CreateReg(*Subreg,
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true /*IsDef*/,
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true /*IsImp*/,
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false /*IsKill*/,
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false /*IsDead*/));
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AllDead = false;
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}
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}
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if(AllDead)
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MO.setIsKill(true);
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return false;
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}
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/// FixupKills - Fix the register kill flags, they may have been made
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/// incorrect by instruction reordering.
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///
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void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
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std::set<unsigned> killedRegs;
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BitVector ReservedRegs = TRI->getReservedRegs(MF);
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StartBlockForKills(MBB);
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// Examine block from end to start...
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unsigned Count = MBB->size();
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for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
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I != E; --Count) {
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MachineInstr *MI = --I;
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if (MI->isDebugValue())
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continue;
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// Update liveness. Registers that are defed but not used in this
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// instruction are now dead. Mark register and all subregs as they
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// are completely defined.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (!MO.isDef()) continue;
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// Ignore two-addr defs.
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if (MI->isRegTiedToUseOperand(i)) continue;
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KillIndices[Reg] = ~0u;
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// Repeat for all subregs.
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg) {
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KillIndices[*Subreg] = ~0u;
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}
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}
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// Examine all used registers and set/clear kill flag. When a
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// register is used multiple times we only set the kill flag on
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// the first use.
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killedRegs.clear();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse()) continue;
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unsigned Reg = MO.getReg();
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if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
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bool kill = false;
|
|
if (killedRegs.find(Reg) == killedRegs.end()) {
|
|
kill = true;
|
|
// A register is not killed if any subregs are live...
|
|
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
|
*Subreg; ++Subreg) {
|
|
if (KillIndices[*Subreg] != ~0u) {
|
|
kill = false;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If subreg is not live, then register is killed if it became
|
|
// live in this instruction
|
|
if (kill)
|
|
kill = (KillIndices[Reg] == ~0u);
|
|
}
|
|
|
|
if (MO.isKill() != kill) {
|
|
DEBUG(dbgs() << "Fixing " << MO << " in ");
|
|
// Warning: ToggleKillFlag may invalidate MO.
|
|
ToggleKillFlag(MI, MO);
|
|
DEBUG(MI->dump());
|
|
}
|
|
|
|
killedRegs.insert(Reg);
|
|
}
|
|
|
|
// Mark any used register (that is not using undef) and subregs as
|
|
// now live...
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
|
|
|
|
KillIndices[Reg] = Count;
|
|
|
|
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
|
*Subreg; ++Subreg) {
|
|
KillIndices[*Subreg] = Count;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Top-Down Scheduling
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
|
|
/// the PendingQueue if the count reaches zero. Also update its cycle bound.
|
|
void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
|
|
SUnit *SuccSU = SuccEdge->getSUnit();
|
|
|
|
#ifndef NDEBUG
|
|
if (SuccSU->NumPredsLeft == 0) {
|
|
dbgs() << "*** Scheduling failed! ***\n";
|
|
SuccSU->dump(this);
|
|
dbgs() << " has been released too many times!\n";
|
|
llvm_unreachable(0);
|
|
}
|
|
#endif
|
|
--SuccSU->NumPredsLeft;
|
|
|
|
// Compute how many cycles it will be before this actually becomes
|
|
// available. This is the max of the start time of all predecessors plus
|
|
// their latencies.
|
|
SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
|
|
|
|
// If all the node's predecessors are scheduled, this node is ready
|
|
// to be scheduled. Ignore the special ExitSU node.
|
|
if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
|
|
PendingQueue.push_back(SuccSU);
|
|
}
|
|
|
|
/// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
|
|
void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
ReleaseSucc(SU, &*I);
|
|
}
|
|
}
|
|
|
|
/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
|
|
/// count of its successors. If a successor pending count is zero, add it to
|
|
/// the Available queue.
|
|
void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
|
|
DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
|
|
DEBUG(SU->dump(this));
|
|
|
|
Sequence.push_back(SU);
|
|
assert(CurCycle >= SU->getDepth() &&
|
|
"Node scheduled above its depth!");
|
|
SU->setDepthToAtLeast(CurCycle);
|
|
|
|
ReleaseSuccessors(SU);
|
|
SU->isScheduled = true;
|
|
AvailableQueue.ScheduledNode(SU);
|
|
}
|
|
|
|
/// ListScheduleTopDown - The main loop of list scheduling for top-down
|
|
/// schedulers.
|
|
void SchedulePostRATDList::ListScheduleTopDown() {
|
|
unsigned CurCycle = 0;
|
|
|
|
// We're scheduling top-down but we're visiting the regions in
|
|
// bottom-up order, so we don't know the hazards at the start of a
|
|
// region. So assume no hazards (this should usually be ok as most
|
|
// blocks are a single region).
|
|
HazardRec->Reset();
|
|
|
|
// Release any successors of the special Entry node.
|
|
ReleaseSuccessors(&EntrySU);
|
|
|
|
// Add all leaves to Available queue.
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
// It is available if it has no predecessors.
|
|
bool available = SUnits[i].Preds.empty();
|
|
if (available) {
|
|
AvailableQueue.push(&SUnits[i]);
|
|
SUnits[i].isAvailable = true;
|
|
}
|
|
}
|
|
|
|
// In any cycle where we can't schedule any instructions, we must
|
|
// stall or emit a noop, depending on the target.
|
|
bool CycleHasInsts = false;
|
|
|
|
// While Available queue is not empty, grab the node with the highest
|
|
// priority. If it is not ready put it back. Schedule the node.
|
|
std::vector<SUnit*> NotReady;
|
|
Sequence.reserve(SUnits.size());
|
|
while (!AvailableQueue.empty() || !PendingQueue.empty()) {
|
|
// Check to see if any of the pending instructions are ready to issue. If
|
|
// so, add them to the available queue.
|
|
unsigned MinDepth = ~0u;
|
|
for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
|
|
if (PendingQueue[i]->getDepth() <= CurCycle) {
|
|
AvailableQueue.push(PendingQueue[i]);
|
|
PendingQueue[i]->isAvailable = true;
|
|
PendingQueue[i] = PendingQueue.back();
|
|
PendingQueue.pop_back();
|
|
--i; --e;
|
|
} else if (PendingQueue[i]->getDepth() < MinDepth)
|
|
MinDepth = PendingQueue[i]->getDepth();
|
|
}
|
|
|
|
DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
|
|
|
|
SUnit *FoundSUnit = 0;
|
|
bool HasNoopHazards = false;
|
|
while (!AvailableQueue.empty()) {
|
|
SUnit *CurSUnit = AvailableQueue.pop();
|
|
|
|
ScheduleHazardRecognizer::HazardType HT =
|
|
HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
|
|
if (HT == ScheduleHazardRecognizer::NoHazard) {
|
|
FoundSUnit = CurSUnit;
|
|
break;
|
|
}
|
|
|
|
// Remember if this is a noop hazard.
|
|
HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
|
|
|
|
NotReady.push_back(CurSUnit);
|
|
}
|
|
|
|
// Add the nodes that aren't ready back onto the available list.
|
|
if (!NotReady.empty()) {
|
|
AvailableQueue.push_all(NotReady);
|
|
NotReady.clear();
|
|
}
|
|
|
|
// If we found a node to schedule...
|
|
if (FoundSUnit) {
|
|
// ... schedule the node...
|
|
ScheduleNodeTopDown(FoundSUnit, CurCycle);
|
|
HazardRec->EmitInstruction(FoundSUnit);
|
|
CycleHasInsts = true;
|
|
} else {
|
|
if (CycleHasInsts) {
|
|
DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
|
|
HazardRec->AdvanceCycle();
|
|
} else if (!HasNoopHazards) {
|
|
// Otherwise, we have a pipeline stall, but no other problem,
|
|
// just advance the current cycle and try again.
|
|
DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
|
|
HazardRec->AdvanceCycle();
|
|
++NumStalls;
|
|
} else {
|
|
// Otherwise, we have no instructions to issue and we have instructions
|
|
// that will fault if we don't do this right. This is the case for
|
|
// processors without pipeline interlocks and other cases.
|
|
DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
|
|
HazardRec->EmitNoop();
|
|
Sequence.push_back(0); // NULL here means noop
|
|
++NumNoops;
|
|
}
|
|
|
|
++CurCycle;
|
|
CycleHasInsts = false;
|
|
}
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
VerifySchedule(/*isBottomUp=*/false);
|
|
#endif
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Public Constructor Functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
FunctionPass *llvm::createPostRAScheduler(CodeGenOpt::Level OptLevel) {
|
|
return new PostRAScheduler(OptLevel);
|
|
}
|