mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d105e18ab6
This patch fixes the error in ARM.td which stated that Cortex-R5 floating point unit can do only single precision, when it can do double as well. Reviewers: rengolin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10769 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240799 91177308-0d34-0410-b5e6-96231b3b80d8
508 lines
26 KiB
TableGen
508 lines
26 KiB
TableGen
//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// ARM Subtarget state.
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//
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def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
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"Thumb mode">;
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def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
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"Use software floating point features.">;
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//===----------------------------------------------------------------------===//
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// ARM Subtarget features.
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//
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def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
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"Enable VFP2 instructions">;
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def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
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"Enable VFP3 instructions",
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[FeatureVFP2]>;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable NEON instructions",
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[FeatureVFP3]>;
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def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
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"Enable Thumb2 instructions">;
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def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
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"Does not support ARM mode execution",
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[ModeThumb]>;
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def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
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"Enable half-precision floating point">;
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def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
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"Enable VFP4 instructions",
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[FeatureVFP3, FeatureFP16]>;
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
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"true", "Enable ARMv8 FP",
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[FeatureVFP4]>;
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def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
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"Restrict VFP3 to 16 double registers">;
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def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
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"Enable divide instructions">;
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def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
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"HasHardwareDivideInARM", "true",
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"Enable divide instructions in ARM mode">;
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def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
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"Enable Thumb2 extract and pack instructions">;
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def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
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"Has data barrier (dmb / dsb) instructions">;
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def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
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"FP compare + branch is slow">;
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def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
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"Floating point unit supports single precision only">;
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def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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"Enable support for Performance Monitor extensions">;
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def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
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"Enable support for TrustZone security extensions">;
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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"Enable support for Cryptography extensions",
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[FeatureNEON]>;
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
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"Enable support for CRC instructions">;
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// Cyclone has preferred instructions for zeroing VFP registers, which can
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// execute in 0 cycles.
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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// Some processors have FP multiply-accumulate instructions that don't
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// play nicely with other VFP / NEON instructions, and it's generally better
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// to just not use them.
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def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
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"Disable VFP / NEON MAC instructions">;
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// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
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def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
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"HasVMLxForwarding", "true",
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"Has multiplier accumulator forwarding">;
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// Some processors benefit from using NEON instructions for scalar
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// single-precision FP operations.
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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"Prefer 32-bit Thumb instrs">;
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/// Some instructions update CPSR partially, which can add false dependency for
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/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
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/// mapped to a separate physical register. Avoid partial CPSR update for these
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/// processors.
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def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
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"AvoidCPSRPartialUpdate", "true",
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"Avoid CPSR partial update for OOO execution">;
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def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
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"AvoidMOVsShifterOperand", "true",
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"Avoid movs instructions with shifter operand">;
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// Some processors perform return stack prediction. CodeGen should avoid issue
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// "normal" call instructions to callees which do not return.
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def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Has return address stack">;
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/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
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def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
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"Supports v7 DSP instructions in Thumb2">;
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// Multiprocessing extension.
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def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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"Supports Multiprocessing extension">;
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// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
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def FeatureVirtualization : SubtargetFeature<"virtualization",
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"HasVirtualization", "true",
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"Supports Virtualization extension",
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[FeatureHWDiv, FeatureHWDivARM]>;
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// M-series ISA
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def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
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"Is microcontroller profile ('M' series)">;
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// R-series ISA
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def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
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"Is realtime profile ('R' series)">;
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// A-series ISA
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def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
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"Is application profile ('A' series)">;
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// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
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// See ARMInstrInfo.td for details.
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def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
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"NaCl trap">;
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// ARM ISAs.
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def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
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"Support ARM v4T instructions">;
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def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
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"Support ARM v5T instructions",
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[HasV4TOps]>;
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def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
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"Support ARM v5TE, v5TEj, and v5TExp instructions",
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[HasV5TOps]>;
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def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
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"Support ARM v6 instructions",
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[HasV5TEOps]>;
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def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
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"Support ARM v6M instructions",
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[HasV6Ops]>;
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def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
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"Support ARM v6k instructions",
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[HasV6Ops]>;
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def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
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"Support ARM v6t2 instructions",
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[HasV6MOps, HasV6KOps, FeatureThumb2]>;
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def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
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"Support ARM v7 instructions",
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[HasV6T2Ops, FeaturePerfMon]>;
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def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
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"Support ARM v8 instructions",
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[HasV7Ops, FeatureVirtualization,
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FeatureMP]>;
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def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
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"Support ARM v8.1a instructions",
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[HasV8Ops, FeatureAClass, FeatureCRC]>;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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//
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include "ARMSchedule.td"
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// ARM processor families.
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def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
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"Cortex-A5 ARM processors",
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[FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding, FeatureT2XtPk,
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FeatureTrustZone, FeatureMP]>;
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def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
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"Cortex-A7 ARM processors",
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[FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding, FeatureT2XtPk,
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FeatureVFP4, FeatureMP,
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FeatureHWDiv, FeatureHWDivARM,
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FeatureTrustZone, FeatureVirtualization]>;
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def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
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"Cortex-A8 ARM processors",
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[FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding, FeatureT2XtPk,
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FeatureTrustZone]>;
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def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
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"Cortex-A9 ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureFP16,
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FeatureAvoidPartialCPSR,
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FeatureTrustZone]>;
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def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
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"Swift ARM processors",
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[FeatureNEONForFP, FeatureT2XtPk,
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FeatureVFP4, FeatureMP, FeatureHWDiv,
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FeatureHWDivARM, FeatureAvoidPartialCPSR,
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FeatureAvoidMOVsShOp,
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FeatureHasSlowFPVMLx, FeatureTrustZone]>;
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def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
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"Cortex-A12 ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureVFP4,
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FeatureHWDiv, FeatureHWDivARM,
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FeatureAvoidPartialCPSR,
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FeatureVirtualization,
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FeatureTrustZone]>;
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// FIXME: It has not been determined if A15 has these features.
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def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
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"Cortex-A15 ARM processors",
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[FeatureT2XtPk, FeatureVFP4,
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FeatureMP, FeatureHWDiv, FeatureHWDivARM,
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FeatureAvoidPartialCPSR,
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FeatureTrustZone, FeatureVirtualization]>;
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def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
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"Cortex-A17 ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureVFP4,
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FeatureHWDiv, FeatureHWDivARM,
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FeatureAvoidPartialCPSR,
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FeatureVirtualization,
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FeatureTrustZone]>;
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors",
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[FeatureHWDiv, FeatureHWDivARM,
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FeatureTrustZone, FeatureT2XtPk,
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FeatureCrypto, FeatureCRC]>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors",
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[FeatureHWDiv, FeatureHWDivARM,
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FeatureTrustZone, FeatureT2XtPk,
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FeatureCrypto, FeatureCRC]>;
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def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
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"Cortex-R4 ARM processors",
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[FeatureHWDiv,
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FeatureAvoidPartialCPSR,
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FeatureDSPThumb2, FeatureT2XtPk,
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HasV7Ops, FeatureDB, FeatureHasRAS,
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FeatureRClass]>;
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def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
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"Cortex-R5 ARM processors",
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[FeatureSlowFPBrcc,
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FeatureHWDiv, FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureAvoidPartialCPSR,
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FeatureT2XtPk]>;
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// FIXME: krait has currently the same features as A9
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// plus VFP4 and hardware division features.
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def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
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"Qualcomm ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureFP16,
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FeatureAvoidPartialCPSR,
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FeatureTrustZone,
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FeatureVFP4,
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FeatureHWDiv,
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FeatureHWDivARM]>;
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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// V4 Processors.
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def : ProcNoItin<"generic", []>;
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def : ProcNoItin<"arm8", []>;
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def : ProcNoItin<"arm810", []>;
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def : ProcNoItin<"strongarm", []>;
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def : ProcNoItin<"strongarm110", []>;
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def : ProcNoItin<"strongarm1100", []>;
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def : ProcNoItin<"strongarm1110", []>;
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// V4T Processors.
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def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
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def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
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def : ProcNoItin<"arm710t", [HasV4TOps]>;
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def : ProcNoItin<"arm720t", [HasV4TOps]>;
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def : ProcNoItin<"arm9", [HasV4TOps]>;
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def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
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def : ProcNoItin<"arm920", [HasV4TOps]>;
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def : ProcNoItin<"arm920t", [HasV4TOps]>;
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def : ProcNoItin<"arm922t", [HasV4TOps]>;
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def : ProcNoItin<"arm940t", [HasV4TOps]>;
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def : ProcNoItin<"ep9312", [HasV4TOps]>;
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// V5T Processors.
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def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
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def : ProcNoItin<"arm1020t", [HasV5TOps]>;
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// V5TE Processors.
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def : ProcNoItin<"arm9e", [HasV5TEOps]>;
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def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm10e", [HasV5TEOps]>;
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def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
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def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
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def : ProcNoItin<"xscale", [HasV5TEOps]>;
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def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
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// V6 Processors.
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def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
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def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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// V6M Processors.
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def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
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FeatureDB, FeatureMClass]>;
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def : Processor<"cortex-m0plus", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
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FeatureDB, FeatureMClass]>;
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def : Processor<"cortex-m1", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
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FeatureDB, FeatureMClass]>;
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def : Processor<"sc000", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
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FeatureDB, FeatureMClass]>;
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// V6K Processors.
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def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6KOps]>;
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def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6KOps]>;
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def : Processor<"mpcore", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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// V6T2 Processors.
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def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
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FeatureDSPThumb2]>;
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def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
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FeatureHasSlowFPVMLx,
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FeatureDSPThumb2]>;
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// V7a Processors.
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// FIXME: A5 has currently the same Schedule model as A8
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def : ProcessorModel<"cortex-a5", CortexA8Model,
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[ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureVFP4, FeatureDSPThumb2,
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FeatureHasRAS, FeatureAClass]>;
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def : ProcessorModel<"cortex-a7", CortexA8Model,
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[ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS,
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FeatureAClass]>;
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def : ProcessorModel<"cortex-a8", CortexA8Model,
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[ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS,
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FeatureAClass]>;
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def : ProcessorModel<"cortex-a9", CortexA9Model,
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[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS, FeatureMP,
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FeatureAClass]>;
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// FIXME: A12 has currently the same Schedule model as A9
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def : ProcessorModel<"cortex-a12", CortexA9Model,
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[ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureMP,
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FeatureHasRAS, FeatureAClass]>;
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// FIXME: A15 has currently the same ProcessorModel as A9.
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def : ProcessorModel<"cortex-a15", CortexA9Model,
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[ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS,
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FeatureAClass]>;
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// FIXME: A17 has currently the same Schedule model as A9
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def : ProcessorModel<"cortex-a17", CortexA9Model,
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[ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureMP,
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FeatureHasRAS, FeatureAClass]>;
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// FIXME: krait has currently the same Schedule model as A9
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def : ProcessorModel<"krait", CortexA9Model,
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[ProcKrait, HasV7Ops,
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FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS,
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FeatureAClass]>;
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// FIXME: R4 has currently the same ProcessorModel as A8.
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def : ProcessorModel<"cortex-r4", CortexA8Model,
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[ProcR4]>;
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|
|
|
// FIXME: R4F has currently the same ProcessorModel as A8.
|
|
def : ProcessorModel<"cortex-r4f", CortexA8Model,
|
|
[ProcR4,
|
|
FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
|
|
FeatureVFP3, FeatureD16]>;
|
|
|
|
// FIXME: R5 has currently the same ProcessorModel as A8.
|
|
def : ProcessorModel<"cortex-r5", CortexA8Model,
|
|
[ProcR5, HasV7Ops, FeatureDB,
|
|
FeatureVFP3, FeatureDSPThumb2,
|
|
FeatureHasRAS,
|
|
FeatureD16, FeatureRClass]>;
|
|
|
|
// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
|
|
def : ProcessorModel<"cortex-r7", CortexA8Model,
|
|
[ProcR5, HasV7Ops, FeatureDB,
|
|
FeatureVFP3, FeatureDSPThumb2,
|
|
FeatureHasRAS, FeatureVFPOnlySP,
|
|
FeatureD16, FeatureMP, FeatureRClass]>;
|
|
|
|
// V7M Processors.
|
|
def : ProcNoItin<"cortex-m3", [HasV7Ops,
|
|
FeatureThumb2, FeatureNoARM, FeatureDB,
|
|
FeatureHWDiv, FeatureMClass]>;
|
|
def : ProcNoItin<"sc300", [HasV7Ops,
|
|
FeatureThumb2, FeatureNoARM, FeatureDB,
|
|
FeatureHWDiv, FeatureMClass]>;
|
|
|
|
// V7EM Processors.
|
|
def : ProcNoItin<"cortex-m4", [HasV7Ops,
|
|
FeatureThumb2, FeatureNoARM, FeatureDB,
|
|
FeatureHWDiv, FeatureDSPThumb2,
|
|
FeatureT2XtPk, FeatureVFP4,
|
|
FeatureVFPOnlySP, FeatureD16,
|
|
FeatureMClass]>;
|
|
def : ProcNoItin<"cortex-m7", [HasV7Ops,
|
|
FeatureThumb2, FeatureNoARM, FeatureDB,
|
|
FeatureHWDiv, FeatureDSPThumb2,
|
|
FeatureT2XtPk, FeatureFPARMv8,
|
|
FeatureD16, FeatureMClass]>;
|
|
|
|
|
|
// Swift uArch Processors.
|
|
def : ProcessorModel<"swift", SwiftModel,
|
|
[ProcSwift, HasV7Ops, FeatureNEON,
|
|
FeatureDB, FeatureDSPThumb2,
|
|
FeatureHasRAS, FeatureAClass]>;
|
|
|
|
// V8 Processors
|
|
def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
|
|
FeatureDB, FeatureFPARMv8,
|
|
FeatureNEON, FeatureDSPThumb2]>;
|
|
def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
|
|
FeatureDB, FeatureFPARMv8,
|
|
FeatureNEON, FeatureDSPThumb2]>;
|
|
// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
|
|
def : ProcNoItin<"cortex-a72", [ProcA57, HasV8Ops, FeatureAClass,
|
|
FeatureDB, FeatureFPARMv8,
|
|
FeatureNEON, FeatureDSPThumb2]>;
|
|
|
|
// Cyclone is very similar to swift
|
|
def : ProcessorModel<"cyclone", SwiftModel,
|
|
[ProcSwift, HasV8Ops, HasV7Ops,
|
|
FeatureCrypto, FeatureFPARMv8,
|
|
FeatureDB,FeatureDSPThumb2,
|
|
FeatureHasRAS, FeatureZCZeroing]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "ARMRegisterInfo.td"
|
|
|
|
include "ARMCallingConv.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "ARMInstrInfo.td"
|
|
|
|
def ARMInstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Declare the target which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def ARMAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "InstPrinter";
|
|
int PassSubtarget = 1;
|
|
int Variant = 0;
|
|
bit isMCAsmWriter = 1;
|
|
}
|
|
|
|
def ARM : Target {
|
|
// Pull in Instruction Info:
|
|
let InstructionSet = ARMInstrInfo;
|
|
let AssemblyWriters = [ARMAsmWriter];
|
|
}
|