mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
08f2d9379c
Patch by: NAKAMURA Takumi git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170142 91177308-0d34-0410-b5e6-96231b3b80d8
665 lines
20 KiB
C++
665 lines
20 KiB
C++
//===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 Implementation of TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "R600InstrInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "AMDGPUSubtarget.h"
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#include "R600Defines.h"
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#include "R600RegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#define GET_INSTRINFO_CTOR
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#include "AMDGPUGenDFAPacketizer.inc"
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using namespace llvm;
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R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
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: AMDGPUInstrInfo(tm),
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RI(tm, *this)
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{ }
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const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
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return RI;
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}
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bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
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}
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bool R600InstrInfo::isVector(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
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}
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void
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R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
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&& AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
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for (unsigned I = 0; I < 4; I++) {
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unsigned SubRegIndex = RI.getSubRegFromChannel(I);
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buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
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RI.getSubReg(DestReg, SubRegIndex),
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RI.getSubReg(SrcReg, SubRegIndex))
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.addReg(DestReg,
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RegState::Define | RegState::Implicit);
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}
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} else {
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// We can't copy vec4 registers
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assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
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&& !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
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MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
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DestReg, SrcReg);
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NewMI->getOperand(getOperandIdx(*NewMI, R600Operands::SRC0))
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.setIsKill(KillSrc);
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}
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}
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MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
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unsigned DstReg, int64_t Imm) const {
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MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
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MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
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MachineInstrBuilder(MI).addImm(Imm);
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MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT
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return MI;
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}
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unsigned R600InstrInfo::getIEQOpcode() const {
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return AMDGPU::SETE_INT;
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}
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bool R600InstrInfo::isMov(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::MOV:
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case AMDGPU::MOV_IMM_F32:
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case AMDGPU::MOV_IMM_I32:
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return true;
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}
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}
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// Some instructions act as place holders to emulate operations that the GPU
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// hardware does automatically. This function can be used to check if
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// an opcode falls into this category.
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bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
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switch (Opcode) {
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default: return false;
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case AMDGPU::RETURN:
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case AMDGPU::RESERVE_REG:
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return true;
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}
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}
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bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::DOT4_r600_pseudo:
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case AMDGPU::DOT4_eg_pseudo:
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return true;
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}
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}
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bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::CUBE_r600_pseudo:
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case AMDGPU::CUBE_r600_real:
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case AMDGPU::CUBE_eg_pseudo:
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case AMDGPU::CUBE_eg_real:
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return true;
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}
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}
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bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
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unsigned TargetFlags = get(Opcode).TSFlags;
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return ((TargetFlags & R600_InstFlag::OP1) |
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(TargetFlags & R600_InstFlag::OP2) |
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(TargetFlags & R600_InstFlag::OP3));
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}
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DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
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const ScheduleDAG *DAG) const {
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const InstrItineraryData *II = TM->getInstrItineraryData();
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return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
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}
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static bool
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isPredicateSetter(unsigned Opcode) {
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switch (Opcode) {
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case AMDGPU::PRED_X:
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return true;
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default:
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return false;
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}
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}
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static MachineInstr *
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findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) {
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while (I != MBB.begin()) {
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--I;
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MachineInstr *MI = I;
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if (isPredicateSetter(MI->getOpcode()))
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return MI;
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}
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return NULL;
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}
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bool
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R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// Most of the following comes from the ARM implementation of AnalyzeBranch
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (static_cast<MachineInstr *>(I)->getOpcode() != AMDGPU::JUMP) {
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return false;
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}
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() ||
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static_cast<MachineInstr *>(--I)->getOpcode() != AMDGPU::JUMP) {
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if (LastOpc == AMDGPU::JUMP) {
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if(!isPredicated(LastInst)) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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} else {
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MachineInstr *predSet = I;
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while (!isPredicateSetter(predSet->getOpcode())) {
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predSet = --I;
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}
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TBB = LastInst->getOperand(0).getMBB();
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Cond.push_back(predSet->getOperand(1));
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Cond.push_back(predSet->getOperand(2));
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Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
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return false;
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}
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}
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return true; // Can't handle indirect branch.
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = I;
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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// If the block ends with a B and a Bcc, handle it.
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if (SecondLastOpc == AMDGPU::JUMP &&
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isPredicated(SecondLastInst) &&
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LastOpc == AMDGPU::JUMP &&
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!isPredicated(LastInst)) {
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MachineInstr *predSet = --I;
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while (!isPredicateSetter(predSet->getOpcode())) {
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predSet = --I;
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}
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TBB = SecondLastInst->getOperand(0).getMBB();
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FBB = LastInst->getOperand(0).getMBB();
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Cond.push_back(predSet->getOperand(1));
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Cond.push_back(predSet->getOperand(2));
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Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
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const MachineInstr *MI = op.getParent();
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switch (MI->getDesc().OpInfo->RegClass) {
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default: // FIXME: fallthrough??
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case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
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case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
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};
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}
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unsigned
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R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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if (FBB == 0) {
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if (Cond.empty()) {
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BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0);
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return 1;
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} else {
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MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
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assert(PredSet && "No previous predicate !");
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addFlag(PredSet, 0, MO_FLAG_PUSH);
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PredSet->getOperand(2).setImm(Cond[1].getImm());
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BuildMI(&MBB, DL, get(AMDGPU::JUMP))
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.addMBB(TBB)
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.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
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return 1;
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}
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} else {
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MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
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assert(PredSet && "No previous predicate !");
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addFlag(PredSet, 0, MO_FLAG_PUSH);
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PredSet->getOperand(2).setImm(Cond[1].getImm());
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BuildMI(&MBB, DL, get(AMDGPU::JUMP))
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.addMBB(TBB)
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.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
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BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB).addReg(0);
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return 2;
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}
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}
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unsigned
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R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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// Note : we leave PRED* instructions there.
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// They may be needed when predicating instructions.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) {
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return 0;
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}
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--I;
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switch (I->getOpcode()) {
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default:
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return 0;
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case AMDGPU::JUMP:
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if (isPredicated(I)) {
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MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
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clearFlag(predSet, 0, MO_FLAG_PUSH);
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}
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I->eraseFromParent();
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break;
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}
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I = MBB.end();
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if (I == MBB.begin()) {
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return 1;
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}
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--I;
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switch (I->getOpcode()) {
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// FIXME: only one case??
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default:
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return 1;
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case AMDGPU::JUMP:
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if (isPredicated(I)) {
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MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
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clearFlag(predSet, 0, MO_FLAG_PUSH);
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}
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I->eraseFromParent();
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break;
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}
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return 2;
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}
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bool
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R600InstrInfo::isPredicated(const MachineInstr *MI) const {
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int idx = MI->findFirstPredOperandIdx();
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if (idx < 0)
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return false;
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unsigned Reg = MI->getOperand(idx).getReg();
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switch (Reg) {
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default: return false;
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case AMDGPU::PRED_SEL_ONE:
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case AMDGPU::PRED_SEL_ZERO:
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case AMDGPU::PREDICATE_BIT:
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return true;
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}
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}
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bool
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R600InstrInfo::isPredicable(MachineInstr *MI) const {
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// XXX: KILL* instructions can be predicated, but they must be the last
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// instruction in a clause, so this means any instructions after them cannot
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// be predicated. Until we have proper support for instruction clauses in the
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// backend, we will mark KILL* instructions as unpredicable.
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if (MI->getOpcode() == AMDGPU::KILLGT) {
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return false;
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} else {
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return AMDGPUInstrInfo::isPredicable(MI);
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}
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}
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bool
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R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCyles,
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unsigned ExtraPredCycles,
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const BranchProbability &Probability) const{
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return true;
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}
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bool
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R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles,
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unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles,
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unsigned ExtraFCycles,
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const BranchProbability &Probability) const {
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return true;
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}
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bool
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R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
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unsigned NumCyles,
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const BranchProbability &Probability)
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const {
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return true;
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}
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bool
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R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const {
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return false;
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}
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bool
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R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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MachineOperand &MO = Cond[1];
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switch (MO.getImm()) {
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case OPCODE_IS_ZERO_INT:
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MO.setImm(OPCODE_IS_NOT_ZERO_INT);
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break;
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case OPCODE_IS_NOT_ZERO_INT:
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MO.setImm(OPCODE_IS_ZERO_INT);
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break;
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case OPCODE_IS_ZERO:
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MO.setImm(OPCODE_IS_NOT_ZERO);
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break;
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case OPCODE_IS_NOT_ZERO:
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MO.setImm(OPCODE_IS_ZERO);
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break;
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default:
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return true;
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}
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MachineOperand &MO2 = Cond[2];
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switch (MO2.getReg()) {
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case AMDGPU::PRED_SEL_ZERO:
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MO2.setReg(AMDGPU::PRED_SEL_ONE);
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break;
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case AMDGPU::PRED_SEL_ONE:
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MO2.setReg(AMDGPU::PRED_SEL_ZERO);
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break;
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default:
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return true;
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}
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return false;
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}
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bool
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R600InstrInfo::DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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return isPredicateSetter(MI->getOpcode());
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}
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bool
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R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const {
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return false;
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}
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bool
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R600InstrInfo::PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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int PIdx = MI->findFirstPredOperandIdx();
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if (PIdx != -1) {
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MachineOperand &PMO = MI->getOperand(PIdx);
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PMO.setReg(Pred[2].getReg());
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MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
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return true;
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}
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return false;
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}
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unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr *MI,
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unsigned *PredCost) const {
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if (PredCost)
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*PredCost = 2;
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return 2;
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}
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MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Opcode,
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unsigned DstReg,
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unsigned Src0Reg,
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unsigned Src1Reg) const {
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MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
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DstReg); // $dst
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if (Src1Reg) {
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MIB.addImm(0) // $update_exec_mask
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.addImm(0); // $update_predicate
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}
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MIB.addImm(1) // $write
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.addImm(0) // $omod
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.addImm(0) // $dst_rel
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.addImm(0) // $dst_clamp
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.addReg(Src0Reg) // $src0
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.addImm(0) // $src0_neg
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.addImm(0) // $src0_rel
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.addImm(0); // $src0_abs
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if (Src1Reg) {
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MIB.addReg(Src1Reg) // $src1
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.addImm(0) // $src1_neg
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.addImm(0) // $src1_rel
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.addImm(0); // $src1_abs
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}
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//XXX: The r600g finalizer expects this to be 1, once we've moved the
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//scheduling to the backend, we can change the default to 0.
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MIB.addImm(1) // $last
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.addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
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.addImm(0); // $literal
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return MIB;
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}
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MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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unsigned DstReg,
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uint64_t Imm) const {
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MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
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AMDGPU::ALU_LITERAL_X);
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setImmOperand(MovImm, R600Operands::IMM, Imm);
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return MovImm;
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}
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int R600InstrInfo::getOperandIdx(const MachineInstr &MI,
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R600Operands::Ops Op) const {
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return getOperandIdx(MI.getOpcode(), Op);
|
|
}
|
|
|
|
int R600InstrInfo::getOperandIdx(unsigned Opcode,
|
|
R600Operands::Ops Op) const {
|
|
const static int OpTable[3][R600Operands::COUNT] = {
|
|
// W C S S S S S S S S
|
|
// R O D L S R R R S R R R S R R L P
|
|
// D U I M R A R C C C C C C C R C C A R I
|
|
// S E U T O E M C 0 0 0 C 1 1 1 C 2 2 S E M
|
|
// T M P E D L P 0 N R A 1 N R A 2 N R T D M
|
|
{0,-1,-1, 1, 2, 3, 4, 5, 6, 7, 8,-1,-1,-1,-1,-1,-1,-1, 9,10,11},
|
|
{0, 1, 2, 3, 4 ,5 ,6 ,7, 8, 9,10,11,12,-1,-1,-1,13,14,15,16,17},
|
|
{0,-1,-1,-1,-1, 1, 2, 3, 4, 5,-1, 6, 7, 8,-1, 9,10,11,12,13,14}
|
|
};
|
|
unsigned TargetFlags = get(Opcode).TSFlags;
|
|
unsigned OpTableIdx;
|
|
|
|
if (!HAS_NATIVE_OPERANDS(TargetFlags)) {
|
|
switch (Op) {
|
|
case R600Operands::DST: return 0;
|
|
case R600Operands::SRC0: return 1;
|
|
case R600Operands::SRC1: return 2;
|
|
case R600Operands::SRC2: return 3;
|
|
default:
|
|
assert(!"Unknown operand type for instruction");
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
if (TargetFlags & R600_InstFlag::OP1) {
|
|
OpTableIdx = 0;
|
|
} else if (TargetFlags & R600_InstFlag::OP2) {
|
|
OpTableIdx = 1;
|
|
} else {
|
|
assert((TargetFlags & R600_InstFlag::OP3) && "OP1, OP2, or OP3 not defined "
|
|
"for this instruction");
|
|
OpTableIdx = 2;
|
|
}
|
|
|
|
return OpTable[OpTableIdx][Op];
|
|
}
|
|
|
|
void R600InstrInfo::setImmOperand(MachineInstr *MI, R600Operands::Ops Op,
|
|
int64_t Imm) const {
|
|
int Idx = getOperandIdx(*MI, Op);
|
|
assert(Idx != -1 && "Operand not supported for this instruction.");
|
|
assert(MI->getOperand(Idx).isImm());
|
|
MI->getOperand(Idx).setImm(Imm);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction flag getters/setters
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
|
|
return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
|
|
}
|
|
|
|
MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
|
|
unsigned Flag) const {
|
|
unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
|
|
int FlagIndex = 0;
|
|
if (Flag != 0) {
|
|
// If we pass something other than the default value of Flag to this
|
|
// function, it means we are want to set a flag on an instruction
|
|
// that uses native encoding.
|
|
assert(HAS_NATIVE_OPERANDS(TargetFlags));
|
|
bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
|
|
switch (Flag) {
|
|
case MO_FLAG_CLAMP:
|
|
FlagIndex = getOperandIdx(*MI, R600Operands::CLAMP);
|
|
break;
|
|
case MO_FLAG_MASK:
|
|
FlagIndex = getOperandIdx(*MI, R600Operands::WRITE);
|
|
break;
|
|
case MO_FLAG_NOT_LAST:
|
|
case MO_FLAG_LAST:
|
|
FlagIndex = getOperandIdx(*MI, R600Operands::LAST);
|
|
break;
|
|
case MO_FLAG_NEG:
|
|
switch (SrcIdx) {
|
|
case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_NEG); break;
|
|
case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_NEG); break;
|
|
case 2: FlagIndex = getOperandIdx(*MI, R600Operands::SRC2_NEG); break;
|
|
}
|
|
break;
|
|
|
|
case MO_FLAG_ABS:
|
|
assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
|
|
"instructions.");
|
|
(void)IsOP3;
|
|
switch (SrcIdx) {
|
|
case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_ABS); break;
|
|
case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_ABS); break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
FlagIndex = -1;
|
|
break;
|
|
}
|
|
assert(FlagIndex != -1 && "Flag not supported for this instruction");
|
|
} else {
|
|
FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
|
|
assert(FlagIndex != 0 &&
|
|
"Instruction flags not supported for this instruction");
|
|
}
|
|
|
|
MachineOperand &FlagOp = MI->getOperand(FlagIndex);
|
|
assert(FlagOp.isImm());
|
|
return FlagOp;
|
|
}
|
|
|
|
void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
|
|
unsigned Flag) const {
|
|
unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
|
|
if (Flag == 0) {
|
|
return;
|
|
}
|
|
if (HAS_NATIVE_OPERANDS(TargetFlags)) {
|
|
MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
|
|
if (Flag == MO_FLAG_NOT_LAST) {
|
|
clearFlag(MI, Operand, MO_FLAG_LAST);
|
|
} else if (Flag == MO_FLAG_MASK) {
|
|
clearFlag(MI, Operand, Flag);
|
|
} else {
|
|
FlagOp.setImm(1);
|
|
}
|
|
} else {
|
|
MachineOperand &FlagOp = getFlagOp(MI, Operand);
|
|
FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
|
|
}
|
|
}
|
|
|
|
void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
|
|
unsigned Flag) const {
|
|
unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
|
|
if (HAS_NATIVE_OPERANDS(TargetFlags)) {
|
|
MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
|
|
FlagOp.setImm(0);
|
|
} else {
|
|
MachineOperand &FlagOp = getFlagOp(MI);
|
|
unsigned InstFlags = FlagOp.getImm();
|
|
InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
|
|
FlagOp.setImm(InstFlags);
|
|
}
|
|
}
|