Petr Pavlu d2e1e42c1a [TableGen] Improve decoding options for non-orthogonal instructions ... When FixedLenDecoder matches an input bitpattern of form [01]+ with an instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are mixed/variable bits) it passes the input bitpattern to a specific instruction decoder method which then makes a final decision whether the bitpattern is a valid instruction or not. This means the decoder must handle all possible values of the variable bits which sometimes leads to opcode rewrites in the decoder method when the instructions are not fully orthogonal. The patch provides a way for the decoder method to say that when it returns Fail it does not necessarily mean the bitpattern is invalid, but rather that the bitpattern is definitely not an instruction that is recognized by the decoder method. The decoder can then try to match the input bitpattern with other possible instruction bitpatterns. For example, this allows to solve a situation on AArch64 where the `MSR (immediate)` instruction has form: 1101 0101 0000 0??? 0100 ???? ???1 1111 but not all values of the ? bits are allowed. The rejected values should be handled by the `extended MSR (register)` instruction: 1101 0101 000? ???? ???? ???? ???? ???? The decoder will first try to decode an input bitpattern that matches both bitpatterns as `MSR (immediate)` but currently this puts the decoder method of `MSR (immediate)` into a situation when it must be able to decode all possible values of the ? bits, i.e. it would need to rewrite the instruction to `MSR (register)` when it is not `MSR (immediate)`. The patch allows to specify that the decoder method cannot determine if the instruction is valid for all variable values. The decoder method can simply return Fail when it knows it is definitely not `MSR (immediate)`. The decoder will then backtrack the decoding and find that it can match the input bitpattern with the more generic `MSR (register)` bitpattern too. Differential Revision: http://reviews.llvm.org/D7174 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242274 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-15 08:04:27 +00:00
..
AsmMatcherEmitter.cpp	Reverting r241058 because it's causing buildbot failures.	2015-06-30 12:32:53 +00:00
AsmWriterEmitter.cpp
AsmWriterInst.cpp
AsmWriterInst.h
CallingConvEmitter.cpp
CMakeLists.txt
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp	Avoid a Symbol -> Name -> Symbol conversion.	2015-06-22 17:46:53 +00:00
CodeGenDAGPatterns.h
CodeGenInstruction.cpp
CodeGenInstruction.h
CodeGenIntrinsics.h
CodeGenMapTable.cpp
CodeGenRegisters.cpp
CodeGenRegisters.h
CodeGenSchedule.cpp
CodeGenSchedule.h
CodeGenTarget.cpp	Rename llvm.frameescape and llvm.framerecover to localescape and localrecover	2015-07-07 22:25:32 +00:00
CodeGenTarget.h
CTagsEmitter.cpp
DAGISelEmitter.cpp
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp
DAGISelMatcherOpt.cpp
DFAPacketizerEmitter.cpp
DisassemblerEmitter.cpp	[TableGen] Improve decoding options for non-orthogonal instructions	2015-07-15 08:04:27 +00:00
FastISelEmitter.cpp
FixedLenDecoderEmitter.cpp	[TableGen] Improve decoding options for non-orthogonal instructions	2015-07-15 08:04:27 +00:00
InstrInfoEmitter.cpp
IntrinsicEmitter.cpp
LLVMBuild.txt
Makefile
module.modulemap
OptParserEmitter.cpp
PseudoLoweringEmitter.cpp
RegisterInfoEmitter.cpp	Target RegisterInfo: devirtualize TargetFrameLowering	2015-07-10 18:13:17 +00:00
SequenceToOffsetTable.h
SubtargetEmitter.cpp	MC: Remove MCSubtargetInfo() default constructor	2015-07-10 22:43:42 +00:00
TableGen.cpp
TableGenBackends.h
tdtags
X86DisassemblerShared.h
X86DisassemblerTables.cpp	AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types.	2015-07-13 13:26:20 +00:00
X86DisassemblerTables.h
X86ModRMFilters.cpp
X86ModRMFilters.h
X86RecognizableInstr.cpp	AVX-512: Added all SKX forms of GATHER instructions.	2015-06-28 10:53:29 +00:00
X86RecognizableInstr.h