Hal Finkel 292c78ba68 Preserve the order of READ_REGISTER and WRITE_REGISTER ... At the present time, we don't have a way to represent general dependency relationships, so everything is represented using memory dependency. In order to preserve the data dependency of a READ_REGISTER on WRITE_REGISTER, we need to model WRITE_REGISTER as writing (which we had been doing) and model READ_REGISTER as reading (which we had not been doing). Fix this, and also the way that the chain operands were generated at the SDAG level. Patch by Nicholas Paul Johnson, thanks! Test case by me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237584 91177308-0d34-0410-b5e6-96231b3b80d8		2015-05-18 16:42:10 +00:00
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AArch64	[PM] Port EarlyCSE to the new pass manager.	2015-02-01 10:51:23 +00:00
basic.ll	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
commute.ll
floatingpoint.ll
instsimplify-dom.ll
read-reg.ll	Preserve the order of READ_REGISTER and WRITE_REGISTER	2015-05-18 16:42:10 +00:00