mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
204 lines
7.5 KiB
LLVM
204 lines
7.5 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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;
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; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
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; much higher than the ADD instructions in order to hide latency. When not
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; specifying a subtarget, the MADD will remain near the end of the block.
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: main
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; CHECK: *** Final schedule for BB#2 ***
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; CHECK: MADDWrrr
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; CHECK: ADDWri
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; CHECK: ********** INTERVALS **********
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@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
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@main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%retval = alloca i32, align 4
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%x = alloca [8 x i32], align 4
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%y = alloca [8 x i32], align 4
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%i = alloca i32, align 4
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%xx = alloca i32, align 4
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%yy = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = bitcast [8 x i32]* %x to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([8 x i32]* @main.x to i8*), i64 32, i32 4, i1 false)
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%1 = bitcast [8 x i32]* %y to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([8 x i32]* @main.y to i8*), i64 32, i32 4, i1 false)
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store i32 0, i32* %xx, align 4
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store i32 0, i32* %yy, align 4
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store i32 0, i32* %i, align 4
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%2 = load i32, i32* %i, align 4
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%cmp = icmp slt i32 %2, 8
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%3 = load i32, i32* %i, align 4
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%idxprom = sext i32 %3 to i64
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%arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* %x, i32 0, i64 %idxprom
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%4 = load i32, i32* %arrayidx, align 4
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%add = add nsw i32 %4, 1
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store i32 %add, i32* %xx, align 4
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%5 = load i32, i32* %xx, align 4
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%add1 = add nsw i32 %5, 12
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store i32 %add1, i32* %xx, align 4
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%6 = load i32, i32* %xx, align 4
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%add2 = add nsw i32 %6, 23
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store i32 %add2, i32* %xx, align 4
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%7 = load i32, i32* %xx, align 4
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%add3 = add nsw i32 %7, 34
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store i32 %add3, i32* %xx, align 4
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%8 = load i32, i32* %i, align 4
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%idxprom4 = sext i32 %8 to i64
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%arrayidx5 = getelementptr inbounds [8 x i32], [8 x i32]* %y, i32 0, i64 %idxprom4
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%9 = load i32, i32* %arrayidx5, align 4
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%10 = load i32, i32* %yy, align 4
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%mul = mul nsw i32 %10, %9
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store i32 %mul, i32* %yy, align 4
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br label %for.inc
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for.inc: ; preds = %for.body
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%11 = load i32, i32* %i, align 4
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%inc = add nsw i32 %11, 1
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store i32 %inc, i32* %i, align 4
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br label %for.cond
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for.end: ; preds = %for.cond
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%12 = load i32, i32* %xx, align 4
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%13 = load i32, i32* %yy, align 4
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%add6 = add nsw i32 %12, %13
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ret i32 %add6
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}
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; The Cortex-A53 machine model will cause the FDIVvvv_42 to be raised to
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; hide latency. Whereas normally there would only be a single FADDvvv_4s
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; after it, this test checks to make sure there are more than one.
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: neon4xfloat:BB#0
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; CHECK: *** Final schedule for BB#0 ***
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; CHECK: FDIVv4f32
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; CHECK: FADDv4f32
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; CHECK: FADDv4f32
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; CHECK: ********** INTERVALS **********
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define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {
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%tmp1 = fadd <4 x float> %A, %B;
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%tmp2 = fadd <4 x float> %A, %tmp1;
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%tmp3 = fadd <4 x float> %A, %tmp2;
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%tmp4 = fadd <4 x float> %A, %tmp3;
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%tmp5 = fadd <4 x float> %A, %tmp4;
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%tmp6 = fadd <4 x float> %A, %tmp5;
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%tmp7 = fadd <4 x float> %A, %tmp6;
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%tmp8 = fadd <4 x float> %A, %tmp7;
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%tmp9 = fdiv <4 x float> %A, %B;
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%tmp10 = fadd <4 x float> %tmp8, %tmp9;
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ret <4 x float> %tmp10
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}
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; Function Attrs: nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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; Regression Test for PR19761
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; [ARM64] Cortex-a53 schedule mode can't handle NEON post-increment load
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;
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; Nothing explicit to check other than llc not crashing.
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define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
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%ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8* %A)
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%tmp = getelementptr i8, i8* %A, i32 32
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store i8* %tmp, i8** %ptr
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ret { <16 x i8>, <16 x i8> } %ld2
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}
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declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8*)
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; Regression Test for PR20057.
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;
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; Cortex-A53 machine model stalls on A53UnitFPMDS contention. Instructions that
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; are otherwise ready are jammed in the pending queue.
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; CHECK: ********** MI Scheduling **********
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; CHECK: testResourceConflict
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; CHECK: *** Final schedule for BB#0 ***
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; CHECK: BRK
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; CHECK: ********** INTERVALS **********
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define void @testResourceConflict(float* %ptr) {
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entry:
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%add1 = fadd float undef, undef
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%mul2 = fmul float undef, undef
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%add3 = fadd float %mul2, undef
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%mul4 = fmul float undef, %add3
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%add5 = fadd float %mul4, undef
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%sub6 = fsub float 0.000000e+00, undef
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%sub7 = fsub float %add5, undef
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%div8 = fdiv float 1.000000e+00, undef
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%mul9 = fmul float %div8, %sub7
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%mul14 = fmul float %sub6, %div8
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%mul10 = fsub float -0.000000e+00, %mul14
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%mul15 = fmul float undef, %div8
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%mul11 = fsub float -0.000000e+00, %mul15
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%mul12 = fmul float 0.000000e+00, %div8
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%mul13 = fmul float %add1, %mul9
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%mul21 = fmul float %add5, %mul11
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%add22 = fadd float %mul13, %mul21
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store float %add22, float* %ptr, align 4
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%mul28 = fmul float %add1, %mul10
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%mul33 = fmul float %add5, %mul12
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%add34 = fadd float %mul33, %mul28
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store float %add34, float* %ptr, align 4
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%mul240 = fmul float undef, %mul9
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%add246 = fadd float %mul240, undef
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store float %add246, float* %ptr, align 4
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%mul52 = fmul float undef, %mul10
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%mul57 = fmul float undef, %mul12
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%add58 = fadd float %mul57, %mul52
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store float %add58, float* %ptr, align 4
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%mul27 = fmul float 0.000000e+00, %mul9
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%mul81 = fmul float undef, %mul10
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%add82 = fadd float %mul27, %mul81
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store float %add82, float* %ptr, align 4
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call void @llvm.trap()
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unreachable
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}
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declare void @llvm.trap()
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; Regression test for PR20057: "permanent hazard"'
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; Resource contention on LDST.
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; CHECK: ********** MI Scheduling **********
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; CHECK: testLdStConflict
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; CHECK: *** Final schedule for BB#1 ***
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; CHECK: LD4Fourv2d
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; CHECK: STRQui
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; CHECK: ********** INTERVALS **********
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define void @testLdStConflict() {
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entry:
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br label %loop
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loop:
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%0 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i8(i8* null)
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%ptr = bitcast i8* undef to <2 x i64>*
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store <2 x i64> zeroinitializer, <2 x i64>* %ptr, align 4
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%ptr1 = bitcast i8* undef to <2 x i64>*
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store <2 x i64> zeroinitializer, <2 x i64>* %ptr1, align 4
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%ptr2 = bitcast i8* undef to <2 x i64>*
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store <2 x i64> zeroinitializer, <2 x i64>* %ptr2, align 4
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%ptr3 = bitcast i8* undef to <2 x i64>*
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store <2 x i64> zeroinitializer, <2 x i64>* %ptr3, align 4
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%ptr4 = bitcast i8* undef to <2 x i64>*
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store <2 x i64> zeroinitializer, <2 x i64>* %ptr4, align 4
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br label %loop
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}
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declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i8(i8*)
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