1
0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-22 07:32:48 +00:00
llvm-6502/test/CodeGen/ARM64/vaddlv.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

27 lines
882 B
LLVM

; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
define i64 @test_vaddlv_s32(<2 x i32> %a1) nounwind readnone {
; CHECK: test_vaddlv_s32
; CHECK: saddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
; CHECK-NEXT: ret
entry:
%vaddlv.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %a1) nounwind
ret i64 %vaddlv.i
}
define i64 @test_vaddlv_u32(<2 x i32> %a1) nounwind readnone {
; CHECK: test_vaddlv_u32
; CHECK: uaddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
; CHECK-NEXT: ret
entry:
%vaddlv.i = tail call i64 @llvm.arm64.neon.uaddlv.i64.v2i32(<2 x i32> %a1) nounwind
ret i64 %vaddlv.i
}
declare i64 @llvm.arm64.neon.uaddlv.i64.v2i32(<2 x i32>) nounwind readnone
declare i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32>) nounwind readnone