mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-01 17:29:33 +00:00
ae3a0be92e
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
667 B
LLVM
22 lines
667 B
LLVM
; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not egrep {\(\(xor\|and\)ps\|movd\)}
|
|
|
|
; These operations should be done in integer registers, eliminating constant
|
|
; pool loads, movd's etc.
|
|
|
|
define i32 @test1(float %x) nounwind {
|
|
entry:
|
|
%tmp2 = fsub float -0.000000e+00, %x ; <float> [#uses=1]
|
|
%tmp210 = bitcast float %tmp2 to i32 ; <i32> [#uses=1]
|
|
ret i32 %tmp210
|
|
}
|
|
|
|
define i32 @test2(float %x) nounwind {
|
|
entry:
|
|
%tmp2 = tail call float @copysignf( float 1.000000e+00, float %x ) nounwind readnone ; <float> [#uses=1]
|
|
%tmp210 = bitcast float %tmp2 to i32 ; <i32> [#uses=1]
|
|
ret i32 %tmp210
|
|
}
|
|
|
|
declare float @copysignf(float, float) nounwind readnone
|
|
|