Jakob Stoklund Olesen a6035773d8 Add TRI::getSubRegIndexLaneMask(). ... Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8		2012-09-11 16:34:08 +00:00
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llvm	Add TRI::getSubRegIndexLaneMask().	2012-09-11 16:34:08 +00:00
llvm-c	Make sure macros in the include subdirectory are not used without being defined.	2012-09-04 17:42:53 +00:00