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Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
204 lines
5.5 KiB
LLVM
204 lines
5.5 KiB
LLVM
; RUN: llc -mtriple=thumbv4t-none--eabi < %s | FileCheck %s --check-prefix=CHECK-V4T
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; RUN: llc -mtriple=thumbv5t-none--eabi < %s | FileCheck %s --check-prefix=CHECK-V5T
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; CHECK-V4T-LABEL: clobberframe
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; CHECK-V5T-LABEL: clobberframe
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define <4 x i32> @clobberframe(<6 x i32>* %p) #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr}
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; CHECK-V4T: sub sp,
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; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr}
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%b = alloca <6 x i32>, align 16
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%a = alloca <4 x i32>, align 16
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%stuff = load <6 x i32>, <6 x i32>* %p, align 16
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store <6 x i32> %stuff, <6 x i32>* %b, align 16
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store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
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%0 = load <4 x i32>, <4 x i32>* %a, align 16
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ret <4 x i32> %0
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; Epilogue
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; --------
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; CHECK-V4T: add sp,
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; CHECK-V4T-NEXT: pop {[[SAVED]]}
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; CHECK-V4T-NEXT: mov r12, r3
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; CHECK-V4T-NEXT: pop {r3}
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; CHECK-V4T-NEXT: mov lr, r3
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; CHECK-V4T-NEXT: mov r3, r12
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; CHECK-V4T: bx lr
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; CHECK-V5T: pop {[[SAVED]], pc}
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}
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; CHECK-V4T-LABEL: clobbervariadicframe
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; CHECK-V5T-LABEL: clobbervariadicframe
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define <4 x i32> @clobbervariadicframe(i32 %i, ...) #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T: sub sp,
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; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr}
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; CHECK-V5T: sub sp,
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; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr}
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%b = alloca <4 x i32>, align 16
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%a = alloca <4 x i32>, align 16
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store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16
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store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
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%0 = load <4 x i32>, <4 x i32>* %a, align 16
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call void @llvm.va_start(i8* null)
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ret <4 x i32> %0
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; Epilogue
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; --------
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; CHECK-V4T: pop {[[SAVED]]}
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; CHECK-V4T-NEXT: mov r12, r3
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; CHECK-V4T-NEXT: pop {r3}
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; CHECK-V4T-NEXT: add sp,
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; CHECK-V4T-NEXT: mov lr, r3
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; CHECK-V4T-NEXT: mov r3, r12
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; CHECK-V4T: bx lr
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; CHECK-V5T: add sp,
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; CHECK-V5T-NEXT: pop {[[SAVED]]}
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; CHECK-V5T-NEXT: mov r12, r3
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; CHECK-V5T-NEXT: pop {r3}
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; CHECK-V5T-NEXT: add sp,
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; CHECK-V5T-NEXT: mov lr, r3
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; CHECK-V5T-NEXT: mov r3, r12
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; CHECK-V5T-NEXT: bx lr
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}
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; CHECK-V4T-LABEL: simpleframe
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; CHECK-V5T-LABEL: simpleframe
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define i32 @simpleframe(<6 x i32>* %p) #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr}
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; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr}
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%0 = load <6 x i32>, <6 x i32>* %p, align 16
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%1 = extractelement <6 x i32> %0, i32 0
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%2 = extractelement <6 x i32> %0, i32 1
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%3 = extractelement <6 x i32> %0, i32 2
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%4 = extractelement <6 x i32> %0, i32 3
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%5 = extractelement <6 x i32> %0, i32 4
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%6 = extractelement <6 x i32> %0, i32 5
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%add1 = add nsw i32 %1, %2
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%add2 = add nsw i32 %add1, %3
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%add3 = add nsw i32 %add2, %4
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%add4 = add nsw i32 %add3, %5
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%add5 = add nsw i32 %add4, %6
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ret i32 %add5
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; Epilogue
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; --------
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; CHECK-V4T: pop {[[SAVED]]}
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; CHECK-V4T: pop {r3}
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; CHECK-V4T: bx r3
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; CHECK-V5T: pop {[[SAVED]], pc}
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}
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; CHECK-V4T-LABEL: simplevariadicframe
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; CHECK-V5T-LABEL: simplevariadicframe
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define i32 @simplevariadicframe(i32 %i, ...) #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T: sub sp,
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; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr}
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; CHECK-V4T: sub sp,
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; CHECK-V5T: sub sp,
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; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr}
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; CHECK-V5T: sub sp,
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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%d = alloca i32, align 4
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store i32 1, i32* %a, align 4
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store i32 2, i32* %b, align 4
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store i32 3, i32* %c, align 4
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store i32 4, i32* %d, align 4
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%0 = load i32, i32* %a, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* %a, align 4
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%1 = load i32, i32* %b, align 4
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%inc1 = add nsw i32 %1, 1
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store i32 %inc1, i32* %b, align 4
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%2 = load i32, i32* %c, align 4
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%inc2 = add nsw i32 %2, 1
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store i32 %inc2, i32* %c, align 4
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%3 = load i32, i32* %d, align 4
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%inc3 = add nsw i32 %3, 1
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store i32 %inc3, i32* %d, align 4
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%4 = load i32, i32* %a, align 4
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%5 = load i32, i32* %b, align 4
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%add = add nsw i32 %4, %5
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%6 = load i32, i32* %c, align 4
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%add4 = add nsw i32 %add, %6
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%7 = load i32, i32* %d, align 4
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%add5 = add nsw i32 %add4, %7
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%add6 = add nsw i32 %add5, %i
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call void @llvm.va_start(i8* null)
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ret i32 %add6
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; Epilogue
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; --------
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; CHECK-V4T: add sp,
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; CHECK-V4T-NEXT: pop {[[SAVED]]}
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; CHECK-V4T-NEXT: pop {r3}
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; CHECK-V4T-NEXT: add sp,
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; CHECK-V4T-NEXT: bx r3
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; CHECK-V5T: add sp,
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; CHECK-V5T-NEXT: pop {[[SAVED]]}
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; CHECK-V5T-NEXT: pop {r3}
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; CHECK-V5T-NEXT: add sp,
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; CHECK-V5T-NEXT: bx r3
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}
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; CHECK-V4T-LABEL: noframe
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; CHECK-V5T-LABEL: noframe
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define i32 @noframe() #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T-NOT: push
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; CHECK-V5T-NOT: push
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ret i32 0;
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; Epilogue
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; --------
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; CHECK-V4T-NOT: pop
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; CHECK-V5T-NOT: pop
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; CHECK-V4T: bx lr
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; CHECK-V5T: bx lr
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}
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; CHECK-V4T-LABEL: novariadicframe
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; CHECK-V5T-LABEL: novariadicframe
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define i32 @novariadicframe(i32 %i, ...) #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T: sub sp,
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; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr}
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; CHECK-V5T: sub sp,
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; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr}
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call void @llvm.va_start(i8* null)
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ret i32 %i;
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; Epilogue
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; --------
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; CHECK-V4T: pop {[[SAVED]]}
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; CHECK-V4T-NEXT: pop {r3}
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; CHECK-V4T-NEXT: add sp,
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; CHECK-V4T-NEXT: bx r3
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; CHECK-V5T: pop {[[SAVED]]}
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; CHECK-V5T-NEXT: pop {r3}
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; CHECK-V5T-NEXT: add sp,
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; CHECK-V5T-NEXT: bx r3
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}
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declare void @llvm.va_start(i8*) nounwind
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