llvm-6502/test/CodeGen/Mips/msa
Daniel Sanders dfce63b1ba [mips] Correct and improve special-case shuffle instructions.
Summary:
The documentation writes vectors highest-index first whereas LLVM-IR writes
them lowest-index first. As a result, instructions defined in terms of
left_half() and right_half() had the halves reversed.

In addition to correcting them, they have been improved to allow shuffles
that use the same operand twice or in reverse order. For example, ilvev
used to accept masks of the form:
  <0, n, 2, n+2, 4, n+4, ...>
but now accepts:
  <0, 0, 2, 2, 4, 4, ...>
  <n, n, n+2, n+2, n+4, n+4, ...>
  <0, n, 2, n+2, 4, n+4, ...>
  <n, 0, n+2, 2, n+4, 4, ...>

One further improvement is that splati.[bhwd] is now the preferred instruction
for splat-like operations. The other special shuffles are no longer used
for splats. This lead to the discovery that <0, 0, ...> would not cause
splati.[hwd] to be selected and this has also been fixed.

This fixes the enc-3des test from the test-suite on Mips64r6 with MSA.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9660

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237689 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-19 12:24:52 +00:00
..
2r_vector_scalar.ll
2r.ll
2rf_exup.ll
2rf_float_int.ll
2rf_fq.ll
2rf_int_float.ll
2rf_tq.ll
2rf.ll
3r_4r_widen.ll
3r_4r.ll
3r_splat.ll
3r-a.ll
3r-b.ll
3r-c.ll
3r-d.ll
3r-i.ll
3r-m.ll
3r-p.ll
3r-s.ll
3r-v.ll
3rf_4rf_q.ll
3rf_4rf.ll
3rf_exdo.ll
3rf_float_int.ll
3rf_int_float.ll
3rf_q.ll
3rf.ll
arithmetic_float.ll
arithmetic.ll
basic_operations_float.ll [mips] Generate code for insert/extract operations when using the N64 ABI and MSA. 2015-05-05 10:32:24 +00:00
basic_operations.ll [mips] Generate code for insert/extract operations when using the N64 ABI and MSA. 2015-05-05 10:32:24 +00:00
bit.ll
bitcast.ll
bitwise.ll
compare_float.ll
compare.ll
elm_copy.ll
elm_cxcmsa.ll
elm_insv.ll
elm_move.ll
elm_shift_slide.ll
endian.ll
frameindex.ll
i5_ld_st.ll
i5-a.ll
i5-b.ll
i5-c.ll
i5-m.ll
i5-s.ll
i8.ll
i10.ll
inline-asm.ll
llvm-stress-s449609655-simplified.ll
llvm-stress-s525530439.ll
llvm-stress-s997348632.ll
llvm-stress-s1704963983.ll
llvm-stress-s1935737938.ll
llvm-stress-s2090927243-simplified.ll
llvm-stress-s2501752154-simplified.ll
llvm-stress-s2704903805.ll
llvm-stress-s3861334421.ll
llvm-stress-s3926023935.ll
llvm-stress-s3997499501.ll
llvm-stress-sz1-s742806235.ll
shift-dagcombine.ll
shuffle.ll [mips] Correct and improve special-case shuffle instructions. 2015-05-19 12:24:52 +00:00
special.ll
spill.ll
vec.ll
vecs10.ll