Bill Wendling a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal ... shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8		2011-03-01 01:00:59 +00:00
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Alpha
ARM	Narrow right shifts need to encode their immediates differently from a normal	2011-03-01 01:00:59 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic	Make this test x86 specific because the ARM backend can't handle it.	2011-02-28 12:30:47 +00:00
MBlaze
Mips
MSP430
PowerPC
PTX	Add preliminary support for .f32 in the PTX backend.	2011-02-28 06:34:09 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	Windows codegen also dies on this, so restrict to the platform it was	2011-02-28 14:22:08 +00:00
XCore	Add XCore intrinsic for eeu instruction.	2011-02-24 13:39:18 +00:00