mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
92bfb54770
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN single and double forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
202 lines
7.1 KiB
LLVM
202 lines
7.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK: LCP
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; CHECK: .long 2
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; CHECK: .long 5
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; CHECK: .long 0
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; CHECK: .long 0
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; CHECK: .long 7
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; CHECK: .long 0
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; CHECK: .long 10
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; CHECK: .long 1
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; CHECK: .long 0
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; CHECK: .long 5
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; CHECK: .long 0
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; CHECK: .long 4
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; CHECK: .long 7
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; CHECK: .long 0
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; CHECK: .long 10
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; CHECK: .long 1
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; CHECK-LABEL: test1:
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; CHECK: vpermps
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; CHECK: ret
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define <16 x float> @test1(<16 x float> %a) nounwind {
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%c = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
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ret <16 x float> %c
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}
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; CHECK-LABEL: test2:
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; CHECK: vpermd
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; CHECK: ret
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define <16 x i32> @test2(<16 x i32> %a) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
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ret <16 x i32> %c
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}
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; CHECK-LABEL: test3:
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; CHECK: vpermq
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; CHECK: ret
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define <8 x i64> @test3(<8 x i64> %a) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 5, i32 1, i32 undef, i32 7, i32 undef, i32 3, i32 1>
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ret <8 x i64> %c
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}
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; CHECK-LABEL: test4:
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; CHECK: vpermpd
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; CHECK: ret
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define <8 x double> @test4(<8 x double> %a) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <8 x double> %c
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}
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; CHECK-LABEL: test5:
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; CHECK: vpermi2pd
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; CHECK: ret
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define <8 x double> @test5(<8 x double> %a, <8 x double> %b) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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ret <8 x double> %c
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}
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; CHECK-LABEL: test6:
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; CHECK: vpermq $30
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; CHECK: ret
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define <8 x i64> @test6(<8 x i64> %a) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 1, i32 0, i32 6, i32 7, i32 5, i32 4>
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ret <8 x i64> %c
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}
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; CHECK-LABEL: test7:
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; CHECK: vpermi2q
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; CHECK: ret
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define <8 x i64> @test7(<8 x i64> %a, <8 x i64> %b) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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ret <8 x i64> %c
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}
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; CHECK-LABEL: test8:
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; CHECK: vpermi2d
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; CHECK: ret
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define <16 x i32> @test8(<16 x i32> %a, <16 x i32> %b) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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ret <16 x i32> %c
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}
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; CHECK-LABEL: test9:
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; CHECK: vpermi2ps
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; CHECK: ret
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define <16 x float> @test9(<16 x float> %a, <16 x float> %b) nounwind {
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%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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ret <16 x float> %c
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}
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; CHECK-LABEL: test10:
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; CHECK: vpermi2ps (
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; CHECK: ret
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define <16 x float> @test10(<16 x float> %a, <16 x float>* %b) nounwind {
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%c = load <16 x float>* %b
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%d = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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ret <16 x float> %d
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}
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; CHECK-LABEL: test11:
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; CHECK: vpermi2d (
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; CHECK: ret
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define <16 x i32> @test11(<16 x i32> %a, <16 x i32>* %b) nounwind {
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%c = load <16 x i32>* %b
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%d = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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ret <16 x i32> %d
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}
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; CHECK-LABEL: test12
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; CHECK: vmovlhpsz %xmm
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; CHECK: ret
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define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) nounwind {
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%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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ret <4 x i32> %c
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}
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; CHECK-LABEL: test13
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; CHECK: vpermilps $-79, %zmm
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; CHECK: ret
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define <16 x float> @test13(<16 x float> %a) {
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%b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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ret <16 x float> %b
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}
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; CHECK-LABEL: test14
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; CHECK: vpermilpd $-53, %zmm
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; CHECK: ret
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define <8 x double> @test14(<8 x double> %a) {
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%b = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32><i32 1, i32 1, i32 2, i32 3, i32 4, i32 4, i32 7, i32 7>
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ret <8 x double> %b
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}
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; CHECK-LABEL: test15
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; CHECK: vpshufd $-79, %zmm
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; CHECK: ret
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define <16 x i32> @test15(<16 x i32> %a) {
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%b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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ret <16 x i32> %b
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}
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; CHECK-LABEL: test16
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; CHECK: valignq $2, %zmm0, %zmm1
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; CHECK: ret
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define <8 x double> @test16(<8 x double> %a, <8 x double> %b) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
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ret <8 x double> %c
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}
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; CHECK-LABEL: test17
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; CHECK: vshufpd $19, %zmm1, %zmm0
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; CHECK: ret
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define <8 x double> @test17(<8 x double> %a, <8 x double> %b) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 9, i32 2, i32 10, i32 5, i32 undef, i32 undef, i32 undef>
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ret <8 x double> %c
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}
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; CHECK-LABEL: test18
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; CHECK: vpunpckhdq %zmm
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; CHECK: ret
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define <16 x i32> @test18(<16 x i32> %a, <16 x i32> %c) {
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%b = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32><i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15, i32 18, i32 26, i32 19, i32 27, i32 22, i32 30, i32 23, i32 31>
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ret <16 x i32> %b
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}
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; CHECK-LABEL: test19
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; CHECK: vpunpckldq %zmm
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; CHECK: ret
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define <16 x i32> @test19(<16 x i32> %a, <16 x i32> %c) {
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%b = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32><i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13, i32 16, i32 24, i32 17, i32 25, i32 20, i32 28, i32 21, i32 29>
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ret <16 x i32> %b
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}
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; CHECK-LABEL: test20
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; CHECK: vpunpckhqdq %zmm
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; CHECK: ret
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define <8 x i64> @test20(<8 x i64> %a, <8 x i64> %c) {
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%b = shufflevector <8 x i64> %a, <8 x i64> %c, <8 x i32><i32 1, i32 5, i32 3, i32 7, i32 9, i32 13, i32 11, i32 15>
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ret <8 x i64> %b
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}
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; CHECK-LABEL: test21
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; CHECK: vunpcklps %zmm
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; CHECK: ret
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define <16 x float> @test21(<16 x float> %a, <16 x float> %c) {
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%b = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32><i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13, i32 16, i32 24, i32 17, i32 25, i32 20, i32 28, i32 21, i32 29>
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ret <16 x float> %b
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}
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; CHECK-LABEL: test22
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; CHECK: vmovhlpsz %xmm
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; CHECK: ret
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define <4 x i32> @test22(<4 x i32> %a, <4 x i32> %b) nounwind {
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%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
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ret <4 x i32> %c
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}
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; CHECK-LABEL: @test23
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; CHECK: vshufps $-112, %zmm
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; CHECK: ret
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define <16 x float> @test23(<16 x float> %a, <16 x float> %c) {
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%b = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32><i32 0, i32 0, i32 17, i32 18, i32 4, i32 4, i32 21, i32 22, i32 8, i32 8, i32 25, i32 26, i32 12, i32 12, i32 29, i32 30>
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ret <16 x float> %b
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} |