Evan Cheng 733c6b1db1 LLVM sdisel normalize bit extraction of the form: ... ((x & 0xff00) >> 8) << 2 to (x >> 6) & 0x3fc This is general goodness since it folds a left shift into the mask. However, the trailing zeros in the mask prevents the ARM backend from using the bit extraction instructions. And worse since the mask materialization may require an addition instruction. This comes up fairly frequently when the result of the bit twiddling is used as memory address. e.g. = ptr[(x & 0xFF0000) >> 16] We want to generate: ubfx r3, r1, #16, #8 ldr.w r3, [r0, r3, lsl #2] vs. mov.w r9, #1020 and.w r2, r9, r1, lsr #14 ldr r2, [r0, r2] Add a late ARM specific isel optimization to ARMDAGToDAGISel::PreprocessISelDAG(). It folds the left shift to the 'base + offset' address computation; change the mask to one which doesn't have trailing zeros and enable the use of ubfx. Note the optimization has to be done late since it's target specific and we don't want to change the DAG normalization. It's also fairly restrictive as shifter operands are not always free. It's only done for lsh 1 / 2. It's known to be free on some cpus and they are most common for address computation. This is a slight win for blowfish, rijndael, etc. rdar://12870177 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170581 91177308-0d34-0410-b5e6-96231b3b80d8		2012-12-19 20:16:09 +00:00
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ARM	LLVM sdisel normalize bit extraction of the form:	2012-12-19 20:16:09 +00:00
CPP
Generic	After reducing the size of an operation in the DAG we zero-extend the reduced	2012-12-19 07:39:08 +00:00
Hexagon	In hexagon convertToHardwareLoop, don't deref end() iterator	2012-12-07 21:03:15 +00:00
MBlaze
Mips	This patch is needed to make c++ exceptions work for mips16.	2012-12-16 04:00:45 +00:00
MSP430
NVPTX
PowerPC	PowerPC: Expand VSELECT nodes.	2012-12-19 15:49:14 +00:00
R600	Add R600 backend	2012-12-11 21:25:42 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC
Thumb
Thumb2
X86	Optimized load + SIGN_EXTEND patterns in the X86 backend.	2012-12-19 07:50:20 +00:00
XCore