mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
55097ff567
Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178460 91177308-0d34-0410-b5e6-96231b3b80d8
330 lines
12 KiB
TableGen
330 lines
12 KiB
TableGen
//===-- ARMSchedule.td - ARM Scheduling Definitions --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction scheduling annotations for out-of-order CPUs.
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// These annotations are independent of the itinerary class defined below.
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// Here we define the subtarget independent read/write per-operand resources.
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// The subtarget schedule definitions will then map these to the subtarget's
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// resource usages.
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// For example:
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// The instruction cycle timings table might contain an entry for an operation
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// like the following:
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// Rd <- ADD Rn, Rm, <shift> Rs
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// Uops | Latency from register | Uops - resource requirements - latency
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// 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
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// | | uopc Rd, Rn, T0 - P01 - 1
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// This is telling us that the result will be available in destination register
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// Rd after a minimum of three cycles after the result in Rm and Rs is available
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// and one cycle after the result in Rn is available. The micro-ops can execute
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// on resource P01.
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// To model this, we need to express that we need to dispatch two micro-ops,
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// that the resource P01 is needed and that the latency to Rn is different than
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// the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
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// two.
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// We will do this by assigning (abstract) resources to register defs/uses.
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// ARMSchedule.td:
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// def WriteALUsr : SchedWrite;
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// def ReadAdvanceALUsr : ScheRead;
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//
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// ARMInstrInfo.td:
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// def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
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// ReadDefault]> { ...}
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// ReadAdvance read resources allow us to define "pipeline by-passes" or
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// shorter latencies to certain registers as needed in the example above.
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// The "ReadDefault" can be omitted.
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// Next, the subtarget td file assigns resources to the abstract resources
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// defined here.
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// ARMScheduleSubtarget.td:
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// // Resources.
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// def P01 : ProcResource<3>; // ALU unit (3 of it).
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// ...
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// // Resource usages.
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// def : WriteRes<WriteALUsr, [P01, P01]> {
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// Latency = 4; // Latency of 4.
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// NumMicroOps = 2; // Dispatch 2 micro-ops.
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// // The two instances of resource P01 are occupied for one cycle. It is one
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// // cycle because these resources happen to be pipelined.
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// ResourceCycles = [1, 1];
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// }
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// def : ReadAdvance<ReadAdvanceALUsr, 3>;
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// Basic ALU operation.
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def WriteALU : SchedWrite;
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def ReadALU : SchedRead;
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// Basic ALU with shifts.
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def WriteALUsi : SchedWrite; // Shift by immediate.
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def WriteALUsr : SchedWrite; // Shift by register.
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def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
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def ReadALUsr : SchedRead; // Some operands are read later.
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// Define TII for use in SchedVariant Predicates.
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def : PredicateProlog<[{
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const ARMBaseInstrInfo *TII =
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static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
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(void)TII;
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}]>;
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for ARM
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//
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def IIC_iALUx : InstrItinClass;
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def IIC_iALUi : InstrItinClass;
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def IIC_iALUr : InstrItinClass;
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def IIC_iALUsi : InstrItinClass;
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def IIC_iALUsir : InstrItinClass;
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def IIC_iALUsr : InstrItinClass;
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def IIC_iBITi : InstrItinClass;
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def IIC_iBITr : InstrItinClass;
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def IIC_iBITsi : InstrItinClass;
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def IIC_iBITsr : InstrItinClass;
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def IIC_iUNAr : InstrItinClass;
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def IIC_iUNAsi : InstrItinClass;
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def IIC_iEXTr : InstrItinClass;
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def IIC_iEXTAr : InstrItinClass;
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def IIC_iEXTAsr : InstrItinClass;
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def IIC_iCMPi : InstrItinClass;
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def IIC_iCMPr : InstrItinClass;
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def IIC_iCMPsi : InstrItinClass;
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def IIC_iCMPsr : InstrItinClass;
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def IIC_iTSTi : InstrItinClass;
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def IIC_iTSTr : InstrItinClass;
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def IIC_iTSTsi : InstrItinClass;
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def IIC_iTSTsr : InstrItinClass;
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def IIC_iMOVi : InstrItinClass;
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def IIC_iMOVr : InstrItinClass;
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def IIC_iMOVsi : InstrItinClass;
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def IIC_iMOVsr : InstrItinClass;
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def IIC_iMOVix2 : InstrItinClass;
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def IIC_iMOVix2addpc : InstrItinClass;
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def IIC_iMOVix2ld : InstrItinClass;
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def IIC_iMVNi : InstrItinClass;
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def IIC_iMVNr : InstrItinClass;
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def IIC_iMVNsi : InstrItinClass;
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def IIC_iMVNsr : InstrItinClass;
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def IIC_iCMOVi : InstrItinClass;
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def IIC_iCMOVr : InstrItinClass;
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def IIC_iCMOVsi : InstrItinClass;
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def IIC_iCMOVsr : InstrItinClass;
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def IIC_iCMOVix2 : InstrItinClass;
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def IIC_iMUL16 : InstrItinClass;
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def IIC_iMAC16 : InstrItinClass;
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def IIC_iMUL32 : InstrItinClass;
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def IIC_iMAC32 : InstrItinClass;
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def IIC_iMUL64 : InstrItinClass;
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def IIC_iMAC64 : InstrItinClass;
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def IIC_iDIV : InstrItinClass;
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def IIC_iLoad_i : InstrItinClass;
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def IIC_iLoad_r : InstrItinClass;
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def IIC_iLoad_si : InstrItinClass;
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def IIC_iLoad_iu : InstrItinClass;
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def IIC_iLoad_ru : InstrItinClass;
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def IIC_iLoad_siu : InstrItinClass;
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def IIC_iLoad_bh_i : InstrItinClass;
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def IIC_iLoad_bh_r : InstrItinClass;
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def IIC_iLoad_bh_si : InstrItinClass;
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def IIC_iLoad_bh_iu : InstrItinClass;
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def IIC_iLoad_bh_ru : InstrItinClass;
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def IIC_iLoad_bh_siu : InstrItinClass;
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def IIC_iLoad_d_i : InstrItinClass;
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def IIC_iLoad_d_r : InstrItinClass;
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def IIC_iLoad_d_ru : InstrItinClass;
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def IIC_iLoad_m : InstrItinClass;
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def IIC_iLoad_mu : InstrItinClass;
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def IIC_iLoad_mBr : InstrItinClass;
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def IIC_iPop : InstrItinClass;
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def IIC_iPop_Br : InstrItinClass;
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def IIC_iLoadiALU : InstrItinClass;
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def IIC_iStore_i : InstrItinClass;
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def IIC_iStore_r : InstrItinClass;
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def IIC_iStore_si : InstrItinClass;
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def IIC_iStore_iu : InstrItinClass;
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def IIC_iStore_ru : InstrItinClass;
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def IIC_iStore_siu : InstrItinClass;
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def IIC_iStore_bh_i : InstrItinClass;
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def IIC_iStore_bh_r : InstrItinClass;
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def IIC_iStore_bh_si : InstrItinClass;
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def IIC_iStore_bh_iu : InstrItinClass;
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def IIC_iStore_bh_ru : InstrItinClass;
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def IIC_iStore_bh_siu : InstrItinClass;
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def IIC_iStore_d_i : InstrItinClass;
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def IIC_iStore_d_r : InstrItinClass;
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def IIC_iStore_d_ru : InstrItinClass;
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def IIC_iStore_m : InstrItinClass;
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def IIC_iStore_mu : InstrItinClass;
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def IIC_Preload : InstrItinClass;
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def IIC_Br : InstrItinClass;
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def IIC_fpSTAT : InstrItinClass;
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def IIC_fpUNA32 : InstrItinClass;
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def IIC_fpUNA64 : InstrItinClass;
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def IIC_fpCMP32 : InstrItinClass;
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def IIC_fpCMP64 : InstrItinClass;
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def IIC_fpCVTSD : InstrItinClass;
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def IIC_fpCVTDS : InstrItinClass;
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def IIC_fpCVTSH : InstrItinClass;
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def IIC_fpCVTHS : InstrItinClass;
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def IIC_fpCVTIS : InstrItinClass;
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def IIC_fpCVTID : InstrItinClass;
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def IIC_fpCVTSI : InstrItinClass;
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def IIC_fpCVTDI : InstrItinClass;
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def IIC_fpMOVIS : InstrItinClass;
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def IIC_fpMOVID : InstrItinClass;
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def IIC_fpMOVSI : InstrItinClass;
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def IIC_fpMOVDI : InstrItinClass;
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def IIC_fpALU32 : InstrItinClass;
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def IIC_fpALU64 : InstrItinClass;
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def IIC_fpMUL32 : InstrItinClass;
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def IIC_fpMUL64 : InstrItinClass;
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def IIC_fpMAC32 : InstrItinClass;
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def IIC_fpMAC64 : InstrItinClass;
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def IIC_fpFMAC32 : InstrItinClass;
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def IIC_fpFMAC64 : InstrItinClass;
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def IIC_fpDIV32 : InstrItinClass;
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def IIC_fpDIV64 : InstrItinClass;
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def IIC_fpSQRT32 : InstrItinClass;
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def IIC_fpSQRT64 : InstrItinClass;
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def IIC_fpLoad32 : InstrItinClass;
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def IIC_fpLoad64 : InstrItinClass;
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def IIC_fpLoad_m : InstrItinClass;
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def IIC_fpLoad_mu : InstrItinClass;
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def IIC_fpStore32 : InstrItinClass;
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def IIC_fpStore64 : InstrItinClass;
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def IIC_fpStore_m : InstrItinClass;
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def IIC_fpStore_mu : InstrItinClass;
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def IIC_VLD1 : InstrItinClass;
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def IIC_VLD1x2 : InstrItinClass;
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def IIC_VLD1x3 : InstrItinClass;
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def IIC_VLD1x4 : InstrItinClass;
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def IIC_VLD1u : InstrItinClass;
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def IIC_VLD1x2u : InstrItinClass;
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def IIC_VLD1x3u : InstrItinClass;
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def IIC_VLD1x4u : InstrItinClass;
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def IIC_VLD1ln : InstrItinClass;
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def IIC_VLD1lnu : InstrItinClass;
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def IIC_VLD1dup : InstrItinClass;
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def IIC_VLD1dupu : InstrItinClass;
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def IIC_VLD2 : InstrItinClass;
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def IIC_VLD2x2 : InstrItinClass;
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def IIC_VLD2u : InstrItinClass;
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def IIC_VLD2x2u : InstrItinClass;
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def IIC_VLD2ln : InstrItinClass;
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def IIC_VLD2lnu : InstrItinClass;
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def IIC_VLD2dup : InstrItinClass;
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def IIC_VLD2dupu : InstrItinClass;
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def IIC_VLD3 : InstrItinClass;
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def IIC_VLD3ln : InstrItinClass;
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def IIC_VLD3u : InstrItinClass;
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def IIC_VLD3lnu : InstrItinClass;
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def IIC_VLD3dup : InstrItinClass;
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def IIC_VLD3dupu : InstrItinClass;
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def IIC_VLD4 : InstrItinClass;
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def IIC_VLD4ln : InstrItinClass;
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def IIC_VLD4u : InstrItinClass;
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def IIC_VLD4lnu : InstrItinClass;
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def IIC_VLD4dup : InstrItinClass;
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def IIC_VLD4dupu : InstrItinClass;
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def IIC_VST1 : InstrItinClass;
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def IIC_VST1x2 : InstrItinClass;
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def IIC_VST1x3 : InstrItinClass;
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def IIC_VST1x4 : InstrItinClass;
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def IIC_VST1u : InstrItinClass;
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def IIC_VST1x2u : InstrItinClass;
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def IIC_VST1x3u : InstrItinClass;
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def IIC_VST1x4u : InstrItinClass;
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def IIC_VST1ln : InstrItinClass;
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def IIC_VST1lnu : InstrItinClass;
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def IIC_VST2 : InstrItinClass;
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def IIC_VST2x2 : InstrItinClass;
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def IIC_VST2u : InstrItinClass;
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def IIC_VST2x2u : InstrItinClass;
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def IIC_VST2ln : InstrItinClass;
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def IIC_VST2lnu : InstrItinClass;
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def IIC_VST3 : InstrItinClass;
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def IIC_VST3u : InstrItinClass;
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def IIC_VST3ln : InstrItinClass;
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def IIC_VST3lnu : InstrItinClass;
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def IIC_VST4 : InstrItinClass;
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def IIC_VST4u : InstrItinClass;
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def IIC_VST4ln : InstrItinClass;
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def IIC_VST4lnu : InstrItinClass;
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def IIC_VUNAD : InstrItinClass;
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def IIC_VUNAQ : InstrItinClass;
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def IIC_VBIND : InstrItinClass;
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def IIC_VBINQ : InstrItinClass;
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def IIC_VPBIND : InstrItinClass;
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def IIC_VFMULD : InstrItinClass;
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def IIC_VFMULQ : InstrItinClass;
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def IIC_VMOV : InstrItinClass;
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def IIC_VMOVImm : InstrItinClass;
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def IIC_VMOVD : InstrItinClass;
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def IIC_VMOVQ : InstrItinClass;
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def IIC_VMOVIS : InstrItinClass;
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def IIC_VMOVID : InstrItinClass;
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def IIC_VMOVISL : InstrItinClass;
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def IIC_VMOVSI : InstrItinClass;
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def IIC_VMOVDI : InstrItinClass;
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def IIC_VMOVN : InstrItinClass;
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def IIC_VPERMD : InstrItinClass;
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def IIC_VPERMQ : InstrItinClass;
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def IIC_VPERMQ3 : InstrItinClass;
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def IIC_VMACD : InstrItinClass;
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def IIC_VMACQ : InstrItinClass;
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def IIC_VFMACD : InstrItinClass;
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def IIC_VFMACQ : InstrItinClass;
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def IIC_VRECSD : InstrItinClass;
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def IIC_VRECSQ : InstrItinClass;
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def IIC_VCNTiD : InstrItinClass;
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def IIC_VCNTiQ : InstrItinClass;
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def IIC_VUNAiD : InstrItinClass;
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def IIC_VUNAiQ : InstrItinClass;
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def IIC_VQUNAiD : InstrItinClass;
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def IIC_VQUNAiQ : InstrItinClass;
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def IIC_VBINiD : InstrItinClass;
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def IIC_VBINiQ : InstrItinClass;
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def IIC_VSUBiD : InstrItinClass;
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def IIC_VSUBiQ : InstrItinClass;
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def IIC_VBINi4D : InstrItinClass;
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def IIC_VBINi4Q : InstrItinClass;
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def IIC_VSUBi4D : InstrItinClass;
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def IIC_VSUBi4Q : InstrItinClass;
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def IIC_VABAD : InstrItinClass;
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def IIC_VABAQ : InstrItinClass;
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def IIC_VSHLiD : InstrItinClass;
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def IIC_VSHLiQ : InstrItinClass;
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def IIC_VSHLi4D : InstrItinClass;
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def IIC_VSHLi4Q : InstrItinClass;
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def IIC_VPALiD : InstrItinClass;
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def IIC_VPALiQ : InstrItinClass;
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def IIC_VMULi16D : InstrItinClass;
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def IIC_VMULi32D : InstrItinClass;
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def IIC_VMULi16Q : InstrItinClass;
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def IIC_VMULi32Q : InstrItinClass;
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def IIC_VMACi16D : InstrItinClass;
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def IIC_VMACi32D : InstrItinClass;
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def IIC_VMACi16Q : InstrItinClass;
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def IIC_VMACi32Q : InstrItinClass;
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def IIC_VEXTD : InstrItinClass;
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def IIC_VEXTQ : InstrItinClass;
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def IIC_VTB1 : InstrItinClass;
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def IIC_VTB2 : InstrItinClass;
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def IIC_VTB3 : InstrItinClass;
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def IIC_VTB4 : InstrItinClass;
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def IIC_VTBX1 : InstrItinClass;
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def IIC_VTBX2 : InstrItinClass;
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def IIC_VTBX3 : InstrItinClass;
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def IIC_VTBX4 : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Processor instruction itineraries.
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include "ARMScheduleV6.td"
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include "ARMScheduleA8.td"
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include "ARMScheduleA9.td"
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include "ARMScheduleSwift.td"
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