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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
173 lines
5.5 KiB
TableGen
173 lines
5.5 KiB
TableGen
//===-- XCoreInstrFormats.td - XCore Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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field bits<32> Inst;
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let Namespace = "XCore";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Size = sz;
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field bits<32> SoftFail = 0;
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}
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// XCore pseudo instructions format
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class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<0, outs, ins, asmstr, pattern> {
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let isPseudo = 1;
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}
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//===----------------------------------------------------------------------===//
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// Instruction formats
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//===----------------------------------------------------------------------===//
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class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc;
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let DecoderMethod = "Decode3RInstruction";
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}
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class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc;
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let DecoderMethod = "Decode2RUSInstruction";
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}
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// 2RUS with bitp operand
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class _F2RUSBitp<bits<5> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: _F2RUS<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "Decode2RUSBitpInstruction";
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}
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class _FL2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _FRU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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}
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class _FLRU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _FU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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}
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class _FLU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _FU10<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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}
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class _FLU10<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc{5-1};
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let Inst{4} = opc{0};
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let DecoderMethod = "Decode2RInstruction";
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}
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// 2R with first operand as both a source and a destination.
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class _F2RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern> : _F2R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "Decode2RSrcDstInstruction";
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}
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// Same as 2R with last two operands swapped
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class _FR2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: _F2R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeR2RInstruction";
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}
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class _FRUS<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc{5-1};
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let Inst{4} = opc{0};
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let DecoderMethod = "DecodeRUSInstruction";
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}
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// RUS with bitp operand
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class _FRUSBitp<bits<6> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: _FRUS<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeRUSBitpInstruction";
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}
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// RUS with first operand as both a source and a destination and a bitp second
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// operand
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class _FRUSSrcDstBitp<bits<6> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: _FRUS<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeRUSSrcDstBitpInstruction";
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}
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class _FL2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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let Inst{31-27} = opc{9-5};
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let Inst{26-20} = 0b1111110;
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let Inst{19-16} = opc{4-1};
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let Inst{15-11} = 0b11111;
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let Inst{4} = opc{0};
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let DecoderMethod = "DecodeL2RInstruction";
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}
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// Same as L2R with last two operands swapped
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class _FLR2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: _FL2R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeLR2RInstruction";
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}
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class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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bits<4> a;
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let Inst{15-11} = opc{5-1};
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let Inst{10-5} = 0b111111;
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let Inst{4} = opc{0};
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let Inst{3-0} = a;
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}
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class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc{9-5};
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let Inst{10-5} = 0b111111;
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let Inst{4-0} = opc{4-0};
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}
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class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _L5R<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _L6R<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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