Richard Sandiford a6e12b5756 [SystemZ] Allow immediate moves to be rematerialized ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185068 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-27 09:38:48 +00:00
..
AArch64	AArch64: remove accidental test output file.	2013-06-18 21:16:53 +00:00
ARM	Add a subtarget feature 'v8' to the ARM backend.	2013-06-26 16:58:26 +00:00
CPP	test commit: remove blank line.	2013-03-14 05:43:59 +00:00
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs	Revert "Adding DIImportedModules to DIScopes."	2013-03-28 02:44:59 +00:00
MBlaze	Remove unnecessary leading comment characters in lit-only file	2013-03-18 22:08:16 +00:00
Mips	[mips] Improve code generation for constant multiplication using shifts, adds and	2013-06-26 18:48:17 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Add support for selecting CUDA vs OCL mode based on triple	2013-06-21 18:51:49 +00:00
PowerPC	[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.	2013-06-13 20:23:34 +00:00
R600	R600: Use new getNamedOperandIdx function generated by TableGen	2013-06-25 21:22:18 +00:00
SI
SPARC	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
SystemZ	[SystemZ] Allow immediate moves to be rematerialized	2013-06-27 09:38:48 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	ARM: allow predicated barriers in Thumb mode	2013-06-26 16:52:32 +00:00
X86	Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector.	2013-06-26 10:55:03 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00