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https://github.com/c64scene-ar/llvm-6502.git
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51458ed09e
RAGreedy::tryAssign will now evict interference from the preferred register even when another register is free. To support this, add the EvictionCost struct that counts how many hints are broken by an eviction. We don't want to break one hint just to satisfy another. Rename canEvict to shouldEvict, and add the first bit of eviction policy that doesn't depend on spill weights: Always make room in the preferred register as long as the evictees can be split and aren't already assigned to their preferred register. Also make the CSR avoidance more accurate. When looking for a cheaper register it is OK to use a new volatile register. Only CSR aliases that have never been used before should be avoided. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
2.6 KiB
LLVM
63 lines
2.6 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
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; Full strength reduction wouldn't reduce register pressure, so LSR should
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; stick with indexing here.
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; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]]
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; CHECK: cvtdq2ps
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; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]]
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; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4)
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; CHECK: addq $4, %rax
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; CHECK: cmpl %eax, (%{{rdx|r8}})
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; CHECK-NEXT: jg
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define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind {
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entry:
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%0 = load i32* %n, align 4
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%1 = icmp sgt i32 %0, 0
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br i1 %1, label %bb, label %return
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bb:
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%indvar = phi i64 [ %indvar.next, %bb ], [ 0, %entry ]
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%tmp = shl i64 %indvar, 2
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%scevgep = getelementptr float* %y, i64 %tmp
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%scevgep9 = bitcast float* %scevgep to <4 x float>*
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%scevgep10 = getelementptr float* %x, i64 %tmp
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%scevgep1011 = bitcast float* %scevgep10 to <4 x float>*
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%2 = load <4 x float>* %scevgep1011, align 16
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%3 = bitcast <4 x float> %2 to <4 x i32>
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%4 = and <4 x i32> %3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
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%5 = bitcast <4 x i32> %4 to <4 x float>
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%6 = and <4 x i32> %3, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%7 = tail call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %5, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) nounwind
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%tmp.i4 = bitcast <4 x float> %7 to <4 x i32>
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%8 = xor <4 x i32> %tmp.i4, <i32 -1, i32 -1, i32 -1, i32 -1>
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%9 = and <4 x i32> %8, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
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%10 = or <4 x i32> %9, %6
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%11 = bitcast <4 x i32> %10 to <4 x float>
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%12 = fadd <4 x float> %2, %11
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%13 = fsub <4 x float> %12, %11
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%14 = tail call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %2, <4 x float> %13, i8 1) nounwind
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%15 = bitcast <4 x float> %14 to <4 x i32>
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%16 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %15) nounwind readnone
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%17 = fadd <4 x float> %13, %16
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%tmp.i = bitcast <4 x float> %17 to <4 x i32>
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%18 = or <4 x i32> %tmp.i, %6
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%19 = bitcast <4 x i32> %18 to <4 x float>
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store <4 x float> %19, <4 x float>* %scevgep9, align 16
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%tmp12 = add i64 %tmp, 4
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%tmp13 = trunc i64 %tmp12 to i32
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%20 = load i32* %n, align 4
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%21 = icmp sgt i32 %20, %tmp13
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%indvar.next = add i64 %indvar, 1
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br i1 %21, label %bb, label %return
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return:
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ret void
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}
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declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
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declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
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