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https://github.com/c64scene-ar/llvm-6502.git
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b6ad2bd511
These tests rely specifically on the names of ELF relocations, let alone any other detail. There's no way they'd work if LLVM was emitting something else by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179376 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.9 KiB
LLVM
63 lines
1.9 KiB
LLVM
;; RUN: llc -mtriple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
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;; RUN: llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s
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; Also take it on a round-trip through llvm-mc to stretch assembly-parsing's legs:
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;; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | \
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;; RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o - | \
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;; RUN: llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s
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@var8 = global i8 0
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@var16 = global i16 0
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@var32 = global i32 0
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@var64 = global i64 0
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define void @loadstore() {
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%val8 = load i8* @var8
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store volatile i8 %val8, i8* @var8
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%val16 = load i16* @var16
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store volatile i16 %val16, i16* @var16
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%val32 = load i32* @var32
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store volatile i32 %val32, i32* @var32
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%val64 = load i64* @var64
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store volatile i64 %val64, i64* @var64
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ret void
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}
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@globaddr = global i64* null
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define void @address() {
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store i64* @var64, i64** @globaddr
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ret void
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}
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; Check we're using EM_AARCH64
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; OBJ: ElfHeader {
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; OBJ: Machine: EM_AARCH64
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; OBJ: }
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; OBJ: Relocations [
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; OBJ: Section (1) .text {
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var8
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST8_ABS_LO12_NC var8
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var16
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST16_ABS_LO12_NC var16
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var32
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST32_ABS_LO12_NC var32
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var64
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST64_ABS_LO12_NC var64
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; This is on the store, so not really important, but it stops the next
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; match working.
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST64_ABS_LO12_NC var64
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; Pure address-calculation against var64
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var64
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; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADD_ABS_LO12_NC var64
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; OBJ: }
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; OBJ: ]
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