llvm-6502/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
Joey Gouly 159b6f1775 Add -mcpu to two X86 tests.
These tests are failing on Haswell CPUs due to different instruction selection.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188908 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 17:14:31 +00:00

58 lines
2.3 KiB
LLVM

; RUN: llc < %s -march=x86 -mcpu=corei7 | grep sarl | not grep esp
define signext i16 @t(i16* %qmatrix, i16* %dct, i16* %acBaseTable, i16* %acExtTable, i16 signext %acBaseRes, i16 signext %acMaskRes, i16 signext %acExtRes, i32* %bitptr, i32* %source, i32 %markerPrefix, i8** %byteptr, i32 %scale, i32 %round, i32 %bits) {
entry:
br label %cond_next127
cond_next127: ; preds = %cond_next391, %entry
%tmp151 = add i32 0, %round ; <i32> [#uses=1]
%tmp153 = ashr i32 %tmp151, %scale ; <i32> [#uses=1]
%tmp158 = xor i32 0, %tmp153 ; <i32> [#uses=1]
%tmp160 = or i32 %tmp158, 0 ; <i32> [#uses=1]
%tmp180181 = sext i16 0 to i32 ; <i32> [#uses=1]
%tmp183 = add i32 %tmp160, 1 ; <i32> [#uses=1]
br i1 false, label %cond_true188, label %cond_next245
cond_true188: ; preds = %cond_next127
ret i16 0
cond_next245: ; preds = %cond_next127
%tmp253444 = lshr i32 %tmp180181, 4 ; <i32> [#uses=1]
%tmp254 = and i32 %tmp253444, 15 ; <i32> [#uses=1]
br i1 false, label %cond_true267, label %cond_next391
cond_true267: ; preds = %cond_next245
%tmp269 = load i8** %byteptr, align 4 ; <i8*> [#uses=3]
%tmp270 = load i8* %tmp269, align 1 ; <i8> [#uses=1]
%tmp270271 = zext i8 %tmp270 to i32 ; <i32> [#uses=1]
%tmp272 = getelementptr i8* %tmp269, i32 1 ; <i8*> [#uses=2]
store i8* %tmp272, i8** %byteptr, align 4
%tmp276 = load i8* %tmp272, align 1 ; <i8> [#uses=1]
%tmp278 = getelementptr i8* %tmp269, i32 2 ; <i8*> [#uses=1]
store i8* %tmp278, i8** %byteptr, align 4
%tmp286 = icmp eq i32 %tmp270271, %markerPrefix ; <i1> [#uses=1]
%cond = icmp eq i8 %tmp276, 0 ; <i1> [#uses=1]
%bothcond = and i1 %tmp286, %cond ; <i1> [#uses=1]
br i1 %bothcond, label %cond_true294, label %cond_next327
cond_true294: ; preds = %cond_true267
ret i16 0
cond_next327: ; preds = %cond_true267
br i1 false, label %cond_true343, label %cond_next391
cond_true343: ; preds = %cond_next327
%tmp345 = load i8** %byteptr, align 4 ; <i8*> [#uses=1]
store i8* null, i8** %byteptr, align 4
store i8* %tmp345, i8** %byteptr, align 4
br label %cond_next391
cond_next391: ; preds = %cond_true343, %cond_next327, %cond_next245
%tmp422445 = add i32 %tmp254, %tmp183 ; <i32> [#uses=1]
%tmp429448 = icmp ult i32 %tmp422445, 63 ; <i1> [#uses=1]
br i1 %tmp429448, label %cond_next127, label %UnifiedReturnBlock
UnifiedReturnBlock: ; preds = %cond_next391
ret i16 0
}