mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
5d96e5a1cc
The damage done by physreg coalescing only depends on the number of instructions the extended physreg live range covers. This fixes PR9438. The heuristic is still luck-based, and physreg coalescing really should be disabled completely. We need a register allocator with better hinting support before that is possible. Convert a test to FileCheck and force spilling by inserting an extra call. The previous spilling behavior was dependent on misguided physreg coalescing decisions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127351 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
889 B
LLVM
23 lines
889 B
LLVM
; RUN: llc -mcpu=yonah < %s
|
|
; PR9438
|
|
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
|
|
target triple = "i386-unknown-freebsd9.0"
|
|
|
|
; The 'call fastcc' ties down %ebx, %ecx, and %edx.
|
|
; A MUL8r ties down %al, leaving no GR32_ABCD registers available.
|
|
; The coalescer can easily overallocate physical registers,
|
|
; and register allocation fails.
|
|
|
|
declare fastcc i8* @save_string(i8* %d, i8* nocapture %s) nounwind
|
|
|
|
define i32 @cvtchar(i8* nocapture %sp) nounwind {
|
|
%temp.i = alloca [2 x i8], align 1
|
|
%tmp1 = load i8* %sp, align 1
|
|
%div = udiv i8 %tmp1, 10
|
|
%rem = urem i8 %div, 10
|
|
%arrayidx.i = getelementptr inbounds [2 x i8]* %temp.i, i32 0, i32 0
|
|
store i8 %rem, i8* %arrayidx.i, align 1
|
|
%call.i = call fastcc i8* @save_string(i8* %sp, i8* %arrayidx.i) nounwind
|
|
ret i32 undef
|
|
}
|