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https://github.com/c64scene-ar/llvm-6502.git
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825b93b2df
Add target specific rules for combining vselect dag nodes into movss/movsd when possible. If the vector type of the vselect dag node in input is either MVT::v4i13 or MVT::v4f32, then try to fold according to rules: 1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B) 2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A) If the vector type of the vselect dag node in input is either MVT::v2i64 or MVT::v2f64 (and we have SSE2), then try to fold according to rules: 3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B) 4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199683 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s
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; Verify that we produce movss instead of blendvps when possible.
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;CHECK-LABEL: vsel_float:
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;CHECK-NOT: blendvps
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;CHECK: movss
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;CHECK: ret
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
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ret <4 x float> %vsel
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}
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;CHECK-LABEL: vsel_4xi8:
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;CHECK-NOT: blendvps
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;CHECK: movss
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;CHECK: ret
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define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2
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ret <4 x i8> %vsel
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}
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; We do not have native support for v8i16 blends and we have to use the
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; blendvb instruction or a sequence of NAND/OR/AND. Make sure that we do not
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; reduce the mask in this case.
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;CHECK-LABEL: vsel_8xi16:
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;CHECK: andps
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;CHECK: andps
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;CHECK: orps
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;CHECK: ret
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define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2
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ret <8 x i16> %vsel
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}
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