mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
fd2b2bd6b3
While it's safe for the X86-specific shift nodes, dag combining will kill generic nodes. Insert an AND to make it safe, isel will nuke it as x86's shift instructions have an implicit AND. Fixes PR16108, which contains a contraption to hit this case in between constant folders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197228 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
2.1 KiB
LLVM
95 lines
2.1 KiB
LLVM
; RUN: llc -mcpu=generic -mtriple=i686-unknown-unknown < %s | FileCheck %s
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define i64 @test1(i32 %xx, i32 %test) nounwind {
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%conv = zext i32 %xx to i64
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%and = and i32 %test, 7
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%sh_prom = zext i32 %and to i64
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%shl = shl i64 %conv, %sh_prom
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ret i64 %shl
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; CHECK-LABEL: test1:
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; CHECK: shll %cl, %eax
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; CHECK: shrl %edx
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; CHECK: xorb $31
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; CHECK: shrl %cl, %edx
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}
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define i64 @test2(i64 %xx, i32 %test) nounwind {
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%and = and i32 %test, 7
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%sh_prom = zext i32 %and to i64
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%shl = shl i64 %xx, %sh_prom
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ret i64 %shl
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; CHECK-LABEL: test2:
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; CHECK: shll %cl, %esi
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; CHECK: shrl %edx
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; CHECK: xorb $31
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; CHECK: shrl %cl, %edx
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; CHECK: orl %esi, %edx
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; CHECK: shll %cl, %eax
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}
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define i64 @test3(i64 %xx, i32 %test) nounwind {
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%and = and i32 %test, 7
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%sh_prom = zext i32 %and to i64
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%shr = lshr i64 %xx, %sh_prom
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ret i64 %shr
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; CHECK-LABEL: test3:
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; CHECK: shrl %cl, %esi
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; CHECK: leal (%edx,%edx), %eax
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; CHECK: xorb $31, %cl
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; CHECK: shll %cl, %eax
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; CHECK: orl %esi, %eax
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; CHECK: shrl %cl, %edx
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}
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define i64 @test4(i64 %xx, i32 %test) nounwind {
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%and = and i32 %test, 7
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%sh_prom = zext i32 %and to i64
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%shr = ashr i64 %xx, %sh_prom
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ret i64 %shr
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; CHECK-LABEL: test4:
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; CHECK: shrl %cl, %esi
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; CHECK: leal (%edx,%edx), %eax
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; CHECK: xorb $31, %cl
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; CHECK: shll %cl, %eax
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; CHECK: orl %esi, %eax
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; CHECK: sarl %cl, %edx
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}
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; PR14668
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define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) {
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%shl = shl <2 x i64> %A, %B
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ret <2 x i64> %shl
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; CHECK: test5
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; CHECK: shl
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; CHECK: shldl
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; CHECK: shl
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; CHECK: shldl
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}
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; PR16108
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define i32 @test6() {
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%x = alloca i32, align 4
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%t = alloca i64, align 8
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store i32 1, i32* %x, align 4
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store i64 1, i64* %t, align 8 ;; DEAD
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%load = load i32* %x, align 4
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%shl = shl i32 %load, 8
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%add = add i32 %shl, -224
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%sh_prom = zext i32 %add to i64
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%shl1 = shl i64 1, %sh_prom
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%cmp = icmp ne i64 %shl1, 4294967296
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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ret i32 1
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if.end: ; preds = %entry
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ret i32 0
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; CHECK-LABEL: test6:
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; CHECK-NOT: andb $31
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; CHECK: sete
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; CHECK: movzbl
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; CHECK: xorl $1
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; CHECK: orl
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}
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