mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
6a7770b7ae
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
193 lines
8.1 KiB
LLVM
193 lines
8.1 KiB
LLVM
; RUN: llc -mtriple=x86_64-darwin -mcpu=generic < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-darwin -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
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; CHECK-LABEL: t:
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; CHECK: movl (%r9,%rax,4), %e{{..}}
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; CHECK-NEXT: decq
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; CHECK-NEXT: jne
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; ATOM-LABEL: t:
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; ATOM: movl (%r9,%r{{.+}},4), %e{{..}}
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; ATOM-NEXT: decq
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; ATOM-NEXT: jne
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@Te0 = external global [256 x i32] ; <[256 x i32]*> [#uses=5]
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@Te1 = external global [256 x i32] ; <[256 x i32]*> [#uses=4]
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@Te3 = external global [256 x i32] ; <[256 x i32]*> [#uses=2]
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define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r) nounwind {
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entry:
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%0 = load i32* %rk, align 4 ; <i32> [#uses=1]
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%1 = getelementptr i32* %rk, i64 1 ; <i32*> [#uses=1]
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%2 = load i32* %1, align 4 ; <i32> [#uses=1]
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%tmp15 = add i32 %r, -1 ; <i32> [#uses=1]
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%tmp.16 = zext i32 %tmp15 to i64 ; <i64> [#uses=2]
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br label %bb
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bb: ; preds = %bb1, %entry
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%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %bb1 ] ; <i64> [#uses=3]
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%s1.0 = phi i32 [ %2, %entry ], [ %56, %bb1 ] ; <i32> [#uses=2]
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%s0.0 = phi i32 [ %0, %entry ], [ %43, %bb1 ] ; <i32> [#uses=2]
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%tmp18 = shl i64 %indvar, 4 ; <i64> [#uses=4]
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%rk26 = bitcast i32* %rk to i8* ; <i8*> [#uses=6]
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%3 = lshr i32 %s0.0, 24 ; <i32> [#uses=1]
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%4 = zext i32 %3 to i64 ; <i64> [#uses=1]
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%5 = getelementptr [256 x i32]* @Te0, i64 0, i64 %4 ; <i32*> [#uses=1]
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%6 = load i32* %5, align 4 ; <i32> [#uses=1]
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%7 = lshr i32 %s1.0, 16 ; <i32> [#uses=1]
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%8 = and i32 %7, 255 ; <i32> [#uses=1]
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%9 = zext i32 %8 to i64 ; <i64> [#uses=1]
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%10 = getelementptr [256 x i32]* @Te1, i64 0, i64 %9 ; <i32*> [#uses=1]
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%11 = load i32* %10, align 4 ; <i32> [#uses=1]
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%ctg2.sum2728 = or i64 %tmp18, 8 ; <i64> [#uses=1]
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%12 = getelementptr i8* %rk26, i64 %ctg2.sum2728 ; <i8*> [#uses=1]
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%13 = bitcast i8* %12 to i32* ; <i32*> [#uses=1]
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%14 = load i32* %13, align 4 ; <i32> [#uses=1]
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%15 = xor i32 %11, %6 ; <i32> [#uses=1]
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%16 = xor i32 %15, %14 ; <i32> [#uses=3]
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%17 = lshr i32 %s1.0, 24 ; <i32> [#uses=1]
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%18 = zext i32 %17 to i64 ; <i64> [#uses=1]
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%19 = getelementptr [256 x i32]* @Te0, i64 0, i64 %18 ; <i32*> [#uses=1]
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%20 = load i32* %19, align 4 ; <i32> [#uses=1]
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%21 = and i32 %s0.0, 255 ; <i32> [#uses=1]
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%22 = zext i32 %21 to i64 ; <i64> [#uses=1]
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%23 = getelementptr [256 x i32]* @Te3, i64 0, i64 %22 ; <i32*> [#uses=1]
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%24 = load i32* %23, align 4 ; <i32> [#uses=1]
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%ctg2.sum2930 = or i64 %tmp18, 12 ; <i64> [#uses=1]
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%25 = getelementptr i8* %rk26, i64 %ctg2.sum2930 ; <i8*> [#uses=1]
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%26 = bitcast i8* %25 to i32* ; <i32*> [#uses=1]
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%27 = load i32* %26, align 4 ; <i32> [#uses=1]
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%28 = xor i32 %24, %20 ; <i32> [#uses=1]
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%29 = xor i32 %28, %27 ; <i32> [#uses=4]
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%30 = lshr i32 %16, 24 ; <i32> [#uses=1]
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%31 = zext i32 %30 to i64 ; <i64> [#uses=1]
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%32 = getelementptr [256 x i32]* @Te0, i64 0, i64 %31 ; <i32*> [#uses=1]
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%33 = load i32* %32, align 4 ; <i32> [#uses=2]
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%exitcond = icmp eq i64 %indvar, %tmp.16 ; <i1> [#uses=1]
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br i1 %exitcond, label %bb2, label %bb1
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bb1: ; preds = %bb
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%ctg2.sum31 = add i64 %tmp18, 16 ; <i64> [#uses=1]
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%34 = getelementptr i8* %rk26, i64 %ctg2.sum31 ; <i8*> [#uses=1]
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%35 = bitcast i8* %34 to i32* ; <i32*> [#uses=1]
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%36 = lshr i32 %29, 16 ; <i32> [#uses=1]
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%37 = and i32 %36, 255 ; <i32> [#uses=1]
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%38 = zext i32 %37 to i64 ; <i64> [#uses=1]
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%39 = getelementptr [256 x i32]* @Te1, i64 0, i64 %38 ; <i32*> [#uses=1]
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%40 = load i32* %39, align 4 ; <i32> [#uses=1]
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%41 = load i32* %35, align 4 ; <i32> [#uses=1]
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%42 = xor i32 %40, %33 ; <i32> [#uses=1]
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%43 = xor i32 %42, %41 ; <i32> [#uses=1]
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%44 = lshr i32 %29, 24 ; <i32> [#uses=1]
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%45 = zext i32 %44 to i64 ; <i64> [#uses=1]
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%46 = getelementptr [256 x i32]* @Te0, i64 0, i64 %45 ; <i32*> [#uses=1]
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%47 = load i32* %46, align 4 ; <i32> [#uses=1]
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%48 = and i32 %16, 255 ; <i32> [#uses=1]
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%49 = zext i32 %48 to i64 ; <i64> [#uses=1]
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%50 = getelementptr [256 x i32]* @Te3, i64 0, i64 %49 ; <i32*> [#uses=1]
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%51 = load i32* %50, align 4 ; <i32> [#uses=1]
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%ctg2.sum32 = add i64 %tmp18, 20 ; <i64> [#uses=1]
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%52 = getelementptr i8* %rk26, i64 %ctg2.sum32 ; <i8*> [#uses=1]
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%53 = bitcast i8* %52 to i32* ; <i32*> [#uses=1]
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%54 = load i32* %53, align 4 ; <i32> [#uses=1]
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%55 = xor i32 %51, %47 ; <i32> [#uses=1]
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%56 = xor i32 %55, %54 ; <i32> [#uses=1]
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%indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1]
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br label %bb
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bb2: ; preds = %bb
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%tmp10 = shl i64 %tmp.16, 4 ; <i64> [#uses=2]
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%ctg2.sum = add i64 %tmp10, 16 ; <i64> [#uses=1]
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%tmp1213 = getelementptr i8* %rk26, i64 %ctg2.sum ; <i8*> [#uses=1]
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%57 = bitcast i8* %tmp1213 to i32* ; <i32*> [#uses=1]
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%58 = and i32 %33, -16777216 ; <i32> [#uses=1]
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%59 = lshr i32 %29, 16 ; <i32> [#uses=1]
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%60 = and i32 %59, 255 ; <i32> [#uses=1]
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%61 = zext i32 %60 to i64 ; <i64> [#uses=1]
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%62 = getelementptr [256 x i32]* @Te1, i64 0, i64 %61 ; <i32*> [#uses=1]
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%63 = load i32* %62, align 4 ; <i32> [#uses=1]
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%64 = and i32 %63, 16711680 ; <i32> [#uses=1]
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%65 = or i32 %64, %58 ; <i32> [#uses=1]
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%66 = load i32* %57, align 4 ; <i32> [#uses=1]
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%67 = xor i32 %65, %66 ; <i32> [#uses=2]
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%68 = lshr i32 %29, 8 ; <i32> [#uses=1]
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%69 = zext i32 %68 to i64 ; <i64> [#uses=1]
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%70 = getelementptr [256 x i32]* @Te0, i64 0, i64 %69 ; <i32*> [#uses=1]
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%71 = load i32* %70, align 4 ; <i32> [#uses=1]
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%72 = and i32 %71, -16777216 ; <i32> [#uses=1]
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%73 = and i32 %16, 255 ; <i32> [#uses=1]
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%74 = zext i32 %73 to i64 ; <i64> [#uses=1]
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%75 = getelementptr [256 x i32]* @Te1, i64 0, i64 %74 ; <i32*> [#uses=1]
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%76 = load i32* %75, align 4 ; <i32> [#uses=1]
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%77 = and i32 %76, 16711680 ; <i32> [#uses=1]
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%78 = or i32 %77, %72 ; <i32> [#uses=1]
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%ctg2.sum25 = add i64 %tmp10, 20 ; <i64> [#uses=1]
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%79 = getelementptr i8* %rk26, i64 %ctg2.sum25 ; <i8*> [#uses=1]
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%80 = bitcast i8* %79 to i32* ; <i32*> [#uses=1]
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%81 = load i32* %80, align 4 ; <i32> [#uses=1]
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%82 = xor i32 %78, %81 ; <i32> [#uses=2]
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%83 = lshr i32 %67, 24 ; <i32> [#uses=1]
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%84 = trunc i32 %83 to i8 ; <i8> [#uses=1]
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store i8 %84, i8* %out, align 1
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%85 = lshr i32 %67, 16 ; <i32> [#uses=1]
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%86 = trunc i32 %85 to i8 ; <i8> [#uses=1]
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%87 = getelementptr i8* %out, i64 1 ; <i8*> [#uses=1]
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store i8 %86, i8* %87, align 1
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%88 = getelementptr i8* %out, i64 4 ; <i8*> [#uses=1]
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%89 = lshr i32 %82, 24 ; <i32> [#uses=1]
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%90 = trunc i32 %89 to i8 ; <i8> [#uses=1]
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store i8 %90, i8* %88, align 1
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%91 = lshr i32 %82, 16 ; <i32> [#uses=1]
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%92 = trunc i32 %91 to i8 ; <i8> [#uses=1]
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%93 = getelementptr i8* %out, i64 5 ; <i8*> [#uses=1]
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store i8 %92, i8* %93, align 1
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ret void
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}
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; Check that DAGCombiner doesn't mess up the IV update when the exiting value
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; is equal to the stride.
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; It must not fold (cmp (add iv, 1), 1) --> (cmp iv, 0).
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; CHECK-LABEL: f:
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; CHECK: %for.body
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; CHECK: incl [[IV:%e..]]
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; CHECK: cmpl $1, [[IV]]
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; CHECK: jne
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; CHECK: ret
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; ATOM-LABEL: f:
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; ATOM: %for.body
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; ATOM: incl [[IV:%e..]]
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; ATOM: cmpl $1, [[IV]]
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; ATOM: jne
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; ATOM: ret
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define i32 @f(i32 %i, i32* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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%cmp4 = icmp eq i32 %i, 1
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br i1 %cmp4, label %for.end, label %for.body.lr.ph
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for.body.lr.ph: ; preds = %entry
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%0 = sext i32 %i to i64
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br label %for.body
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for.body: ; preds = %for.body.lr.ph, %for.body
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%indvars.iv = phi i64 [ %0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
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%bi.06 = phi i32 [ 0, %for.body.lr.ph ], [ %i.addr.0.bi.0, %for.body ]
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%b.05 = phi i32 [ 0, %for.body.lr.ph ], [ %.b.0, %for.body ]
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%arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
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%1 = load i32* %arrayidx, align 4
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%cmp1 = icmp ugt i32 %1, %b.05
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%.b.0 = select i1 %cmp1, i32 %1, i32 %b.05
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%2 = trunc i64 %indvars.iv to i32
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%i.addr.0.bi.0 = select i1 %cmp1, i32 %2, i32 %bi.06
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, 1
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%bi.0.lcssa = phi i32 [ 0, %entry ], [ %i.addr.0.bi.0, %for.body ]
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ret i32 %bi.0.lcssa
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}
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