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https://github.com/c64scene-ar/llvm-6502.git
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6a7770b7ae
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.6 KiB
LLVM
58 lines
1.6 KiB
LLVM
; RUN-disabled: llc < %s -mtriple=x86_64-apple-macosx -pre-RA-sched=ilp -debug-only=pre-RA-sched \
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; RUN-disabled: 2>&1 | FileCheck %s
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; RUN: true
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; REQUIRES: asserts
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;
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; rdar:13279013: pre-RA-sched should not check all interferences and
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; repush them on the ready queue after scheduling each instruction.
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;
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; CHECK: *** List Scheduling
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; CHECK: Interfering reg EFLAGS
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; CHECK: Repushing
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; CHECK: Repushing
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; CHECK: Repushing
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; CHECK-NOT: Repushing
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; CHECK: *** Final schedule
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define i32 @test(i8* %pin) #0 {
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%g0 = getelementptr inbounds i8* %pin, i64 0
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%l0 = load i8* %g0, align 1
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%g1a = getelementptr inbounds i8* %pin, i64 1
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%l1a = load i8* %g1a, align 1
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%z1a = zext i8 %l1a to i32
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%g1b = getelementptr inbounds i8* %pin, i64 2
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%l1b = load i8* %g1b, align 1
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%z1b = zext i8 %l1b to i32
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%c1 = icmp ne i8 %l0, 0
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%x1 = xor i32 %z1a, %z1b
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%s1 = select i1 %c1, i32 %z1a, i32 %x1
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%g2a = getelementptr inbounds i8* %pin, i64 3
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%l2a = load i8* %g2a, align 1
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%z2a = zext i8 %l2a to i32
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%g2b = getelementptr inbounds i8* %pin, i64 4
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%l2b = load i8* %g2b, align 1
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%z2b = zext i8 %l2b to i32
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%x2 = xor i32 %z2a, %z2b
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%s2 = select i1 %c1, i32 %z2a, i32 %x2
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%g3a = getelementptr inbounds i8* %pin, i64 5
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%l3a = load i8* %g3a, align 1
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%z3a = zext i8 %l3a to i32
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%g3b = getelementptr inbounds i8* %pin, i64 6
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%l3b = load i8* %g3b, align 1
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%z3b = zext i8 %l3b to i32
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%x3 = xor i32 %z3a, %z3b
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%s3 = select i1 %c1, i32 %z3a, i32 %x3
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%c3 = icmp ne i8 %l1a, 0
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%c4 = icmp ne i8 %l2a, 0
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%s4 = select i1 %c3, i32 %s1, i32 %s2
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%s5 = select i1 %c4, i32 %s4, i32 %s3
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ret i32 %s5
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}
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attributes #0 = { nounwind ssp uwtable }
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