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https://github.com/c64scene-ar/llvm-6502.git
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bf53841cfe
As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane, vector select could be simplified to AND/OR or removed if one or both values being selected is all 0s or all 1s. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179267 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
2.0 KiB
LLVM
73 lines
2.0 KiB
LLVM
; RUN: opt < %s -O3 | \
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; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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define <4 x i32> @test1(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
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%f = fcmp ult <4 x float> %a, %b
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%r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> zeroinitializer
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ret <4 x i32> %r
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; CHECK: test1
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; CHECK: cmpnle
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; CHECK-NEXT: andps
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; CHECK: ret
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}
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define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
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%f = fcmp ult <4 x float> %a, %b
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%r = select <4 x i1> %f, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c
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ret <4 x i32> %r
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; CHECK: test2
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; CHECK: cmpnle
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; CHECK-NEXT: orps
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; CHECK: ret
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}
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define <4 x i32> @test3(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
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%f = fcmp ult <4 x float> %a, %b
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%r = select <4 x i1> %f, <4 x i32> zeroinitializer, <4 x i32> %c
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ret <4 x i32> %r
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; CHECK: test3
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; CHECK: cmple
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; CHECK-NEXT: andps
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; CHECK: ret
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}
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define <4 x i32> @test4(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
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%f = fcmp ult <4 x float> %a, %b
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%r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %r
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; CHECK: test4
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; CHECK: cmple
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; CHECK-NEXT: orps
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; CHECK: ret
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}
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define <4 x i32> @test5(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
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%f = fcmp ult <4 x float> %a, %b
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%r = select <4 x i1> %f, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer
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ret <4 x i32> %r
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; CHECK: test5
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; CHECK: cmpnle
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; CHECK-NEXT: ret
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}
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define <4 x i32> @test6(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
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%f = fcmp ult <4 x float> %a, %b
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%r = select <4 x i1> %f, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %r
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; CHECK: test6
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; CHECK: cmple
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; CHECK-NEXT: ret
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}
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define <4 x i32> @test7(<4 x float> %a, <4 x float> %b, <4 x i32>* %p) {
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%f = fcmp ult <4 x float> %a, %b
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%s = sext <4 x i1> %f to <4 x i32>
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%l = load <4 x i32>* %p
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%r = and <4 x i32> %l, %s
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ret <4 x i32> %r
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; CHECK: test7
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; CHECK: cmpnle
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; CHECK-NEXT: andps
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; CHECK: ret
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}
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