mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
4b3fcc21ec
immediately after SSE scalar fp instructions like addss or mulss.
Added patterns to select SSE scalar fp arithmetic instructions from a scalar
fp operation followed by a blend.
For example, given the following code:
__m128 foo(__m128 A, __m128 B) {
A[0] += B[0];
return A;
}
previously we generated:
addss %xmm0, %xmm1
movss %xmm1, %xmm0
now we generate:
addss %xmm1, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196925 91177308-0d34-0410-b5e6-96231b3b80d8
311 lines
8.2 KiB
LLVM
311 lines
8.2 KiB
LLVM
; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7 < %s | FileCheck -check-prefix=CHECK -check-prefix=SSE2 %s
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; RUN: llc -mtriple=x86_64-pc-linux -mattr=-sse4.1 -mcpu=corei7 < %s | FileCheck -check-prefix=CHECK -check-prefix=SSE2 %s
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; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7-avx < %s | FileCheck -check-prefix=CHECK -check-prefix=AVX %s
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; Ensure that the backend no longer emits unnecessary vector insert
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; instructions immediately after SSE scalar fp instructions
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; like addss or mulss.
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define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %b, i32 0
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%2 = extractelement <4 x float> %a, i32 0
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%add = fadd float %2, %1
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%3 = insertelement <4 x float> %a, float %add, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test_add_ss
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; SSE2: addss %xmm1, %xmm0
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; AVX: vaddss %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %b, i32 0
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%2 = extractelement <4 x float> %a, i32 0
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%sub = fsub float %2, %1
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%3 = insertelement <4 x float> %a, float %sub, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test_sub_ss
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; SSE2: subss %xmm1, %xmm0
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; AVX: vsubss %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %b, i32 0
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%2 = extractelement <4 x float> %a, i32 0
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%mul = fmul float %2, %1
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%3 = insertelement <4 x float> %a, float %mul, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test_mul_ss
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; SSE2: mulss %xmm1, %xmm0
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; AVX: vmulss %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %b, i32 0
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%2 = extractelement <4 x float> %a, i32 0
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%div = fdiv float %2, %1
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%3 = insertelement <4 x float> %a, float %div, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test_div_ss
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; SSE2: divss %xmm1, %xmm0
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; AVX: vdivss %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
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%1 = extractelement <2 x double> %b, i32 0
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%2 = extractelement <2 x double> %a, i32 0
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%add = fadd double %2, %1
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%3 = insertelement <2 x double> %a, double %add, i32 0
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ret <2 x double> %3
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}
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; CHECK-LABEL: test_add_sd
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; SSE2: addsd %xmm1, %xmm0
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; AVX: vaddsd %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {
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%1 = extractelement <2 x double> %b, i32 0
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%2 = extractelement <2 x double> %a, i32 0
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%sub = fsub double %2, %1
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%3 = insertelement <2 x double> %a, double %sub, i32 0
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ret <2 x double> %3
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}
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; CHECK-LABEL: test_sub_sd
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; SSE2: subsd %xmm1, %xmm0
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; AVX: vsubsd %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {
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%1 = extractelement <2 x double> %b, i32 0
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%2 = extractelement <2 x double> %a, i32 0
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%mul = fmul double %2, %1
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%3 = insertelement <2 x double> %a, double %mul, i32 0
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ret <2 x double> %3
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}
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; CHECK-LABEL: test_mul_sd
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; SSE2: mulsd %xmm1, %xmm0
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; AVX: vmulsd %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
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%1 = extractelement <2 x double> %b, i32 0
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%2 = extractelement <2 x double> %a, i32 0
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%div = fdiv double %2, %1
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%3 = insertelement <2 x double> %a, double %div, i32 0
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ret <2 x double> %3
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}
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; CHECK-LABEL: test_div_sd
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; SSE2: divsd %xmm1, %xmm0
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; AVX: vdivsd %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <4 x float> @test2_add_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %a, i32 0
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%2 = extractelement <4 x float> %b, i32 0
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%add = fadd float %1, %2
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%3 = insertelement <4 x float> %b, float %add, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test2_add_ss
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; SSE2: addss %xmm0, %xmm1
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; AVX: vaddss %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test2_sub_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %a, i32 0
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%2 = extractelement <4 x float> %b, i32 0
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%sub = fsub float %2, %1
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%3 = insertelement <4 x float> %b, float %sub, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test2_sub_ss
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; SSE2: subss %xmm0, %xmm1
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; AVX: vsubss %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test2_mul_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %a, i32 0
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%2 = extractelement <4 x float> %b, i32 0
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%mul = fmul float %1, %2
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%3 = insertelement <4 x float> %b, float %mul, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test2_mul_ss
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; SSE2: mulss %xmm0, %xmm1
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; AVX: vmulss %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test2_div_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %a, i32 0
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%2 = extractelement <4 x float> %b, i32 0
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%div = fdiv float %2, %1
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%3 = insertelement <4 x float> %b, float %div, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test2_div_ss
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; SSE2: divss %xmm0, %xmm1
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; AVX: vdivss %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <2 x double> @test2_add_sd(<2 x double> %a, <2 x double> %b) {
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%1 = extractelement <2 x double> %a, i32 0
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%2 = extractelement <2 x double> %b, i32 0
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%add = fadd double %1, %2
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%3 = insertelement <2 x double> %b, double %add, i32 0
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ret <2 x double> %3
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}
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; CHECK-LABEL: test2_add_sd
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; SSE2: addsd %xmm0, %xmm1
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; AVX: vaddsd %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test2_sub_sd(<2 x double> %a, <2 x double> %b) {
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%1 = extractelement <2 x double> %a, i32 0
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%2 = extractelement <2 x double> %b, i32 0
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%sub = fsub double %2, %1
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%3 = insertelement <2 x double> %b, double %sub, i32 0
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ret <2 x double> %3
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}
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; CHECK-LABEL: test2_sub_sd
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; SSE2: subsd %xmm0, %xmm1
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; AVX: vsubsd %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test2_mul_sd(<2 x double> %a, <2 x double> %b) {
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%1 = extractelement <2 x double> %a, i32 0
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%2 = extractelement <2 x double> %b, i32 0
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%mul = fmul double %1, %2
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%3 = insertelement <2 x double> %b, double %mul, i32 0
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ret <2 x double> %3
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}
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; CHECK-LABEL: test2_mul_sd
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; SSE2: mulsd %xmm0, %xmm1
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; AVX: vmulsd %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test2_div_sd(<2 x double> %a, <2 x double> %b) {
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%1 = extractelement <2 x double> %a, i32 0
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%2 = extractelement <2 x double> %b, i32 0
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%div = fdiv double %2, %1
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%3 = insertelement <2 x double> %b, double %div, i32 0
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ret <2 x double> %3
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}
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; CHECK-LABEL: test2_div_sd
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; SSE2: divsd %xmm0, %xmm1
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; AVX: vdivsd %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <4 x float> @test_multiple_add_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %b, i32 0
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%2 = extractelement <4 x float> %a, i32 0
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%add = fadd float %2, %1
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%add2 = fadd float %2, %add
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%3 = insertelement <4 x float> %a, float %add2, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test_multiple_add_ss
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; CHECK: addss
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; CHECK: addss
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test_multiple_sub_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %b, i32 0
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%2 = extractelement <4 x float> %a, i32 0
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%sub = fsub float %2, %1
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%sub2 = fsub float %2, %sub
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%3 = insertelement <4 x float> %a, float %sub2, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test_multiple_sub_ss
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; CHECK: subss
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; CHECK: subss
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test_multiple_mul_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %b, i32 0
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%2 = extractelement <4 x float> %a, i32 0
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%mul = fmul float %2, %1
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%mul2 = fmul float %2, %mul
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%3 = insertelement <4 x float> %a, float %mul2, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test_multiple_mul_ss
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; CHECK: mulss
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; CHECK: mulss
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test_multiple_div_ss(<4 x float> %a, <4 x float> %b) {
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%1 = extractelement <4 x float> %b, i32 0
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%2 = extractelement <4 x float> %a, i32 0
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%div = fdiv float %2, %1
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%div2 = fdiv float %2, %div
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%3 = insertelement <4 x float> %a, float %div2, i32 0
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ret <4 x float> %3
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}
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; CHECK-LABEL: test_multiple_div_ss
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; CHECK: divss
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; CHECK: divss
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; CHECK-NOT: movss
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; CHECK: ret
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