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https://github.com/c64scene-ar/llvm-6502.git
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825b93b2df
Add target specific rules for combining vselect dag nodes into movss/movsd when possible. If the vector type of the vselect dag node in input is either MVT::v4i13 or MVT::v4f32, then try to fold according to rules: 1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B) 2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A) If the vector type of the vselect dag node in input is either MVT::v2i64 or MVT::v2f64 (and we have SSE2), then try to fold according to rules: 3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B) 4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199683 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.5 KiB
LLVM
58 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=yonah -mattr=+sse2,-sse4.1 | FileCheck %s
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; CHECK-LABEL: vsel_float
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK-NOT: orps
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; CHECK: ret
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define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) {
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%A = load <4 x float>* %v1
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%B = load <4 x float>* %v2
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%vsel = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %A, <4 x float> %B
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store <4 x float > %vsel, <4 x float>* %v1
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ret void
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}
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; CHECK-LABEL: vsel_i32
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK-NOT: orps
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; CHECK: ret
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define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) {
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%A = load <4 x i32>* %v1
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%B = load <4 x i32>* %v2
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B
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store <4 x i32 > %vsel, <4 x i32>* %v1
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ret void
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}
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; Without forcing instructions, fall back to the preferred PS domain.
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; CHECK-LABEL: vsel_i64
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; CHECK: andnps
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; CHECK: orps
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; CHECK: ret
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define void@vsel_i64(<2 x i64>* %v1, <2 x i64>* %v2) {
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%A = load <2 x i64>* %v1
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%B = load <2 x i64>* %v2
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %A, <2 x i64> %B
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store <2 x i64 > %vsel, <2 x i64>* %v1
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ret void
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}
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; Without forcing instructions, fall back to the preferred PS domain.
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; CHECK-LABEL: vsel_double
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; CHECK: andnps
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; CHECK: orps
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; CHECK: ret
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define void@vsel_double(<2 x double>* %v1, <2 x double>* %v2) {
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%A = load <2 x double>* %v1
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%B = load <2 x double>* %v2
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %A, <2 x double> %B
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store <2 x double > %vsel, <2 x double>* %v1
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ret void
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}
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