mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
1d82537762
the instruction defenitions and ISEL reflect this. Prior to this patch these instructions took an i32i8imm, and the high bits were dropped during encoding. This led to incorrect behavior for shifts by immediates higher than 255. This patch fixes that issue by detecting large immediate shifts and returning constant zero (for logical shifts) or capping the shift amount at an encodable value (for arithmetic shifts). Fixes <rdar://problem/14968098> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193096 91177308-0d34-0410-b5e6-96231b3b80d8
248 lines
5.4 KiB
LLVM
248 lines
5.4 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 -mcpu=corei7 | FileCheck %s
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; SSE2 Logical Shift Left
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define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
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entry:
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%shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <8 x i16> %shl
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}
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; CHECK-LABEL: test_sllw_1:
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; CHECK: psllw $0, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
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entry:
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%shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <8 x i16> %shl
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}
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; CHECK-LABEL: test_sllw_2:
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; CHECK: paddw %xmm0, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
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entry:
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%shl = shl <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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ret <8 x i16> %shl
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}
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; CHECK-LABEL: test_sllw_3:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
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entry:
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%shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %shl
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}
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; CHECK-LABEL: test_slld_1:
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; CHECK: pslld $0, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
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entry:
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%shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %shl
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}
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; CHECK-LABEL: test_slld_2:
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; CHECK: paddd %xmm0, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
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entry:
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%shl = shl <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32>
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ret <4 x i32> %shl
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}
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; CHECK-LABEL: test_slld_3:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: ret
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define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
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entry:
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%shl = shl <2 x i64> %InVec, <i64 0, i64 0>
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ret <2 x i64> %shl
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}
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; CHECK-LABEL: test_sllq_1:
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; CHECK: psllq $0, %xmm0
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; CHECK-NEXT: ret
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define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
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entry:
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%shl = shl <2 x i64> %InVec, <i64 1, i64 1>
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ret <2 x i64> %shl
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}
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; CHECK-LABEL: test_sllq_2:
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; CHECK: paddq %xmm0, %xmm0
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; CHECK-NEXT: ret
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define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
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entry:
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%shl = shl <2 x i64> %InVec, <i64 64, i64 64>
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ret <2 x i64> %shl
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}
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; CHECK-LABEL: test_sllq_3:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: ret
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; SSE2 Arithmetic Shift
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define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
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entry:
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%shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <8 x i16> %shl
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}
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; CHECK-LABEL: test_sraw_1:
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; CHECK: psraw $0, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
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entry:
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%shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <8 x i16> %shl
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}
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; CHECK-LABEL: test_sraw_2:
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; CHECK: psraw $1, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
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entry:
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%shl = ashr <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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ret <8 x i16> %shl
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}
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; CHECK-LABEL: test_sraw_3:
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; CHECK: psraw $15, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
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entry:
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%shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %shl
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}
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; CHECK-LABEL: test_srad_1:
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; CHECK: psrad $0, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
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entry:
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%shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %shl
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}
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; CHECK-LABEL: test_srad_2:
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; CHECK: psrad $1, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
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entry:
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%shl = ashr <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32>
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ret <4 x i32> %shl
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}
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; CHECK-LABEL: test_srad_3:
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; CHECK: psrad $31, %xmm0
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; CHECK-NEXT: ret
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; SSE Logical Shift Right
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define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
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entry:
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%shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <8 x i16> %shl
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}
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; CHECK-LABEL: test_srlw_1:
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; CHECK: psrlw $0, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
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entry:
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%shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <8 x i16> %shl
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}
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; CHECK-LABEL: test_srlw_2:
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; CHECK: psrlw $1, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
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entry:
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%shl = lshr <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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ret <8 x i16> %shl
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}
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; CHECK-LABEL: test_srlw_3:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
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entry:
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%shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %shl
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}
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; CHECK-LABEL: test_srld_1:
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; CHECK: psrld $0, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
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entry:
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%shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %shl
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}
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; CHECK-LABEL: test_srld_2:
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; CHECK: psrld $1, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
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entry:
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%shl = lshr <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32>
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ret <4 x i32> %shl
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}
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; CHECK-LABEL: test_srld_3:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: ret
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define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
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entry:
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%shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
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ret <2 x i64> %shl
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}
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; CHECK-LABEL: test_srlq_1:
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; CHECK: psrlq $0, %xmm0
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; CHECK-NEXT: ret
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define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
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entry:
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%shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
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ret <2 x i64> %shl
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}
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; CHECK-LABEL: test_srlq_2:
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; CHECK: psrlq $1, %xmm0
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; CHECK-NEXT: ret
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define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
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entry:
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%shl = lshr <2 x i64> %InVec, <i64 64, i64 64>
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ret <2 x i64> %shl
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}
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; CHECK-LABEL: test_srlq_3:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: ret
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