llvm-6502/test/CodeGen/X86/vselect-2.ll
Andrea Di Biagio 106b79744b [X86] Add extra rules for combining vselect dag nodes into movsd.
This improves the fix committed at revision 199683 adding the
following new target specific combine rules:

1) fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
        (v4i32 (bitcast (movsd (v2i64 (bitcast A)), (v2i64 (bitcast B))) ))

2) fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
        (v4f32 (bitcast (movsd (v2f64 (bitcast A)), (v2f64 (bitcast B))) ))

3) fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
        (v4i32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))

4) fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
        (v4f32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200324 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 18:14:21 +00:00

34 lines
1020 B
LLVM

; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=sse2 | FileCheck %s
define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
%select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B
ret <4 x i32> %select
}
; CHECK-LABEL: test1
; CHECK: movsd
; CHECK: ret
define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
%select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x i32> %A, <4 x i32> %B
ret <4 x i32> %select
}
; CHECK-LABEL: test2
; CHECK: movsd
; CHECK-NEXT: ret
define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
%select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x float> %A, <4 x float> %B
ret <4 x float> %select
}
; CHECK-LABEL: test3
; CHECK: movsd
; CHECK: ret
define <4 x float> @test4(<4 x float> %A, <4 x float> %B) {
%select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x float> %A, <4 x float> %B
ret <4 x float> %select
}
; CHECK-LABEL: test4
; CHECK: movsd
; CHECK-NEXT: ret