mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
825b93b2df
Add target specific rules for combining vselect dag nodes into movss/movsd when possible. If the vector type of the vselect dag node in input is either MVT::v4i13 or MVT::v4f32, then try to fold according to rules: 1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B) 2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A) If the vector type of the vselect dag node in input is either MVT::v2i64 or MVT::v2f64 (and we have SSE2), then try to fold according to rules: 3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B) 4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199683 91177308-0d34-0410-b5e6-96231b3b80d8
265 lines
7.0 KiB
LLVM
265 lines
7.0 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
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; Verify that we don't emit packed vector shifts instructions if the
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; condition used by the vector select is a vector of constants.
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test1
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test4
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: movaps %xmm1, %xmm0
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; CHECK: ret
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define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test7
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test8
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test9
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: movaps %xmm1, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test10
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test11
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test12
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
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define <4 x float> @test14(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 undef, i1 true, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test14
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: pcmpeq
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; CHECK: ret
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define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test15
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: pcmpeq
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; CHECK: ret
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; Fold (vselect (build_vector AllZeros), N1, N2) -> N2
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define <4 x float> @test16(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 false, i1 undef, i1 false, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test16
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: ret
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define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 undef, i1 undef, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test17
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: ret
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define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test18
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK: ret
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define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
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%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test19
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK: ret
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define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
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%1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
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ret <2 x double> %1
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}
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; CHECK-LABEL: test20
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK: ret
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define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
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%1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test21
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK: ret
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define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test22
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK: ret
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define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
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%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test23
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK: ret
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define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
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%1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
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ret <2 x double> %1
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}
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; CHECK-LABEL: test24
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK: ret
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define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
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%1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test25
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK: ret
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