mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-20 09:30:43 +00:00
572645cf84
bug fixes, and with improved heuristics for analyzing foreign-loop addrecs. This change also flattens IVUsers, eliminating the stride-oriented groupings, which makes it easier to work with. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95975 91177308-0d34-0410-b5e6-96231b3b80d8
387 lines
11 KiB
LLVM
387 lines
11 KiB
LLVM
; RUN: llc < %s -march=x86-64 -O3 | FileCheck %s
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target datalayout = "e-p:64:64:64"
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target triple = "x86_64-unknown-unknown"
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; Full strength reduction reduces register pressure from 5 to 4 here.
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; Instruction selection should use the FLAGS value from the dec for
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; the branch. Scheduling should push the adds upwards.
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; CHECK: full_me_0:
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; CHECK: movsd (%rsi), %xmm0
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; CHECK: addq $8, %rsi
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; CHECK: mulsd (%rdx), %xmm0
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; CHECK: addq $8, %rdx
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; CHECK: movsd %xmm0, (%rdi)
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; CHECK: addq $8, %rdi
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; CHECK: decq %rcx
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; CHECK: jne
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define void @full_me_0(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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%Ai = getelementptr inbounds double* %A, i64 %i
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%Bi = getelementptr inbounds double* %B, i64 %i
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%Ci = getelementptr inbounds double* %C, i64 %i
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%t1 = load double* %Bi
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%t2 = load double* %Ci
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%m = fmul double %t1, %t2
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store double %m, double* %Ai
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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ret void
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}
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; Mostly-full strength reduction means we do full strength reduction on all
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; except for the offsets.
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;
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; Given a choice between constant offsets -2048 and 2048, choose the negative
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; value, because at boundary conditions it has a smaller encoding.
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; TODO: That's an over-general heuristic. It would be better for the target
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; to indicate what the encoding cost would be. Then using a 2048 offset
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; would be better on x86-64, since the start value would be 0 instead of
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; 2048.
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; CHECK: mostly_full_me_0:
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; CHECK: movsd -2048(%rsi), %xmm0
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; CHECK: mulsd -2048(%rdx), %xmm0
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; CHECK: movsd %xmm0, -2048(%rdi)
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; CHECK: movsd (%rsi), %xmm0
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; CHECK: addq $8, %rsi
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; CHECK: divsd (%rdx), %xmm0
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; CHECK: addq $8, %rdx
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; CHECK: movsd %xmm0, (%rdi)
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; CHECK: addq $8, %rdi
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; CHECK: decq %rcx
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; CHECK: jne
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define void @mostly_full_me_0(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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%Ai = getelementptr inbounds double* %A, i64 %i
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%Bi = getelementptr inbounds double* %B, i64 %i
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%Ci = getelementptr inbounds double* %C, i64 %i
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%t1 = load double* %Bi
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%t2 = load double* %Ci
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%m = fmul double %t1, %t2
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store double %m, double* %Ai
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%j = add i64 %i, 256
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%Aj = getelementptr inbounds double* %A, i64 %j
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%Bj = getelementptr inbounds double* %B, i64 %j
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%Cj = getelementptr inbounds double* %C, i64 %j
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%t3 = load double* %Bj
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%t4 = load double* %Cj
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%o = fdiv double %t3, %t4
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store double %o, double* %Aj
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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ret void
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}
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; A minor variation on mostly_full_me_0.
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; Prefer to start the indvar at 0.
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; CHECK: mostly_full_me_1:
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; CHECK: movsd (%rsi), %xmm0
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; CHECK: mulsd (%rdx), %xmm0
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; CHECK: movsd %xmm0, (%rdi)
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; CHECK: movsd -2048(%rsi), %xmm0
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; CHECK: addq $8, %rsi
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; CHECK: divsd -2048(%rdx), %xmm0
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; CHECK: addq $8, %rdx
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; CHECK: movsd %xmm0, -2048(%rdi)
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; CHECK: addq $8, %rdi
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; CHECK: decq %rcx
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; CHECK: jne
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define void @mostly_full_me_1(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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%Ai = getelementptr inbounds double* %A, i64 %i
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%Bi = getelementptr inbounds double* %B, i64 %i
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%Ci = getelementptr inbounds double* %C, i64 %i
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%t1 = load double* %Bi
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%t2 = load double* %Ci
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%m = fmul double %t1, %t2
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store double %m, double* %Ai
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%j = sub i64 %i, 256
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%Aj = getelementptr inbounds double* %A, i64 %j
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%Bj = getelementptr inbounds double* %B, i64 %j
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%Cj = getelementptr inbounds double* %C, i64 %j
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%t3 = load double* %Bj
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%t4 = load double* %Cj
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%o = fdiv double %t3, %t4
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store double %o, double* %Aj
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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ret void
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}
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; A slightly less minor variation on mostly_full_me_0.
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; CHECK: mostly_full_me_2:
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; CHECK: movsd (%rsi), %xmm0
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; CHECK: mulsd (%rdx), %xmm0
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; CHECK: movsd %xmm0, (%rdi)
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; CHECK: movsd -4096(%rsi), %xmm0
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; CHECK: addq $8, %rsi
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; CHECK: divsd -4096(%rdx), %xmm0
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; CHECK: addq $8, %rdx
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; CHECK: movsd %xmm0, -4096(%rdi)
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; CHECK: addq $8, %rdi
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; CHECK: decq %rcx
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; CHECK: jne
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define void @mostly_full_me_2(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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%k = add i64 %i, 256
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%Ak = getelementptr inbounds double* %A, i64 %k
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%Bk = getelementptr inbounds double* %B, i64 %k
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%Ck = getelementptr inbounds double* %C, i64 %k
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%t1 = load double* %Bk
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%t2 = load double* %Ck
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%m = fmul double %t1, %t2
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store double %m, double* %Ak
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%j = sub i64 %i, 256
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%Aj = getelementptr inbounds double* %A, i64 %j
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%Bj = getelementptr inbounds double* %B, i64 %j
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%Cj = getelementptr inbounds double* %C, i64 %j
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%t3 = load double* %Bj
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%t4 = load double* %Cj
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%o = fdiv double %t3, %t4
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store double %o, double* %Aj
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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ret void
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}
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; In this test, the counting IV exit value is used, so full strength reduction
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; would not reduce register pressure. IndVarSimplify ought to simplify such
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; cases away, but it's useful here to verify that LSR's register pressure
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; heuristics are working as expected.
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; CHECK: count_me_0:
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; CHECK: movsd (%rsi,%rax,8), %xmm0
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; CHECK: mulsd (%rdx,%rax,8), %xmm0
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; CHECK: movsd %xmm0, (%rdi,%rax,8)
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; CHECK: incq %rax
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; CHECK: cmpq %rax, %rcx
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; CHECK: jne
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define i64 @count_me_0(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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%Ai = getelementptr inbounds double* %A, i64 %i
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%Bi = getelementptr inbounds double* %B, i64 %i
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%Ci = getelementptr inbounds double* %C, i64 %i
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%t1 = load double* %Bi
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%t2 = load double* %Ci
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%m = fmul double %t1, %t2
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store double %m, double* %Ai
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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%q = phi i64 [ 0, %entry ], [ %i.next, %loop ]
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ret i64 %q
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}
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; In this test, the trip count value is used, so full strength reduction
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; would not reduce register pressure.
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; (though it would reduce register pressure inside the loop...)
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; CHECK: count_me_1:
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; CHECK: movsd (%rsi,%rax,8), %xmm0
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; CHECK: mulsd (%rdx,%rax,8), %xmm0
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; CHECK: movsd %xmm0, (%rdi,%rax,8)
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; CHECK: incq %rax
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; CHECK: cmpq %rax, %rcx
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; CHECK: jne
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define i64 @count_me_1(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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%Ai = getelementptr inbounds double* %A, i64 %i
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%Bi = getelementptr inbounds double* %B, i64 %i
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%Ci = getelementptr inbounds double* %C, i64 %i
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%t1 = load double* %Bi
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%t2 = load double* %Ci
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%m = fmul double %t1, %t2
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store double %m, double* %Ai
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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%q = phi i64 [ 0, %entry ], [ %n, %loop ]
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ret i64 %q
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}
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; Full strength reduction doesn't save any registers here because the
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; loop tripcount is a constant.
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; CHECK: count_me_2:
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; CHECK: movl $10, %eax
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; CHECK: align
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; CHECK: BB7_1:
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; CHECK: movsd -40(%rdi,%rax,8), %xmm0
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; CHECK: addsd -40(%rsi,%rax,8), %xmm0
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; CHECK: movsd %xmm0, -40(%rdx,%rax,8)
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; CHECK: movsd (%rdi,%rax,8), %xmm0
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; CHECK: subsd (%rsi,%rax,8), %xmm0
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; CHECK: movsd %xmm0, (%rdx,%rax,8)
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; CHECK: incq %rax
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; CHECK: cmpq $5010, %rax
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; CHECK: jne
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define void @count_me_2(double* nocapture %A, double* nocapture %B, double* nocapture %C) nounwind {
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entry:
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br label %loop
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loop:
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%i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
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%i5 = add i64 %i, 5
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%Ai = getelementptr double* %A, i64 %i5
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%t2 = load double* %Ai
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%Bi = getelementptr double* %B, i64 %i5
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%t4 = load double* %Bi
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%t5 = fadd double %t2, %t4
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%Ci = getelementptr double* %C, i64 %i5
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store double %t5, double* %Ci
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%i10 = add i64 %i, 10
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%Ai10 = getelementptr double* %A, i64 %i10
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%t9 = load double* %Ai10
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%Bi10 = getelementptr double* %B, i64 %i10
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%t11 = load double* %Bi10
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%t12 = fsub double %t9, %t11
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%Ci10 = getelementptr double* %C, i64 %i10
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store double %t12, double* %Ci10
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%i.next = add i64 %i, 1
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%exitcond = icmp eq i64 %i.next, 5000
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br i1 %exitcond, label %return, label %loop
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return:
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ret void
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}
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; This should be fully strength-reduced to reduce register pressure.
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; CHECK: full_me_1:
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; CHECK: align
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; CHECK: BB8_1:
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; CHECK: movsd (%rdi), %xmm0
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; CHECK: addsd (%rsi), %xmm0
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; CHECK: movsd %xmm0, (%rdx)
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; CHECK: movsd 40(%rdi), %xmm0
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; CHECK: addq $8, %rdi
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; CHECK: subsd 40(%rsi), %xmm0
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; CHECK: addq $8, %rsi
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; CHECK: movsd %xmm0, 40(%rdx)
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; CHECK: addq $8, %rdx
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; CHECK: decq %rcx
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; CHECK: jne
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define void @full_me_1(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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br label %loop
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loop:
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%i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
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%i5 = add i64 %i, 5
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%Ai = getelementptr double* %A, i64 %i5
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%t2 = load double* %Ai
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%Bi = getelementptr double* %B, i64 %i5
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%t4 = load double* %Bi
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%t5 = fadd double %t2, %t4
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%Ci = getelementptr double* %C, i64 %i5
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store double %t5, double* %Ci
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%i10 = add i64 %i, 10
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%Ai10 = getelementptr double* %A, i64 %i10
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%t9 = load double* %Ai10
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%Bi10 = getelementptr double* %B, i64 %i10
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%t11 = load double* %Bi10
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%t12 = fsub double %t9, %t11
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%Ci10 = getelementptr double* %C, i64 %i10
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store double %t12, double* %Ci10
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%i.next = add i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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ret void
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}
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; This is a variation on full_me_0 in which the 0,+,1 induction variable
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; has a non-address use, pinning that value in a register.
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; CHECK: count_me_3:
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; CHECK: call
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; CHECK: movsd (%r15,%r13,8), %xmm0
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; CHECK: mulsd (%r14,%r13,8), %xmm0
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; CHECK: movsd %xmm0, (%r12,%r13,8)
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; CHECK: incq %r13
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; CHECK: cmpq %r13, %rbx
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; CHECK: jne
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declare void @use(i64)
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define void @count_me_3(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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call void @use(i64 %i)
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%Ai = getelementptr inbounds double* %A, i64 %i
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%Bi = getelementptr inbounds double* %B, i64 %i
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%Ci = getelementptr inbounds double* %C, i64 %i
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%t1 = load double* %Bi
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%t2 = load double* %Ci
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%m = fmul double %t1, %t2
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store double %m, double* %Ai
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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ret void
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}
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