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df4b35e3dd
This also enables domain swizzling for AVX code which required a few trivial test changes. The pass will be moved to lib/CodeGen shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140659 91177308-0d34-0410-b5e6-96231b3b80d8
106 lines
3.5 KiB
LLVM
106 lines
3.5 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; RUN: llc -O0 < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s -check-prefix=CHECK_O0
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; CHECK: vmovaps
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; CHECK: vmovaps
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; CHECK: vmovaps
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; CHECK: vmovaps
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; CHECK: vmovaps
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; CHECK: vmovaps
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define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>* nocapture %i) nounwind uwtable ssp {
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entry:
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%0 = bitcast double* %d to <4 x double>*
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%tmp1.i = load <4 x double>* %0, align 32
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%1 = bitcast float* %f to <8 x float>*
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%tmp1.i17 = load <8 x float>* %1, align 32
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%tmp1.i16 = load <4 x i64>* %i, align 32
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tail call void @dummy(<4 x double> %tmp1.i, <8 x float> %tmp1.i17, <4 x i64> %tmp1.i16) nounwind
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store <4 x double> %tmp1.i, <4 x double>* %0, align 32
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store <8 x float> %tmp1.i17, <8 x float>* %1, align 32
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store <4 x i64> %tmp1.i16, <4 x i64>* %i, align 32
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ret void
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}
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declare void @dummy(<4 x double>, <8 x float>, <4 x i64>)
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;;
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;; The two tests below check that we must fold load + scalar_to_vector
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;; + ins_subvec+ zext into only a single vmovss or vmovsd
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; CHECK: vmovss (%
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define <8 x float> @mov00(<8 x float> %v, float * %ptr) nounwind {
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%val = load float* %ptr
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%i0 = insertelement <8 x float> zeroinitializer, float %val, i32 0
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ret <8 x float> %i0
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}
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; CHECK: vmovsd (%
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define <4 x double> @mov01(<4 x double> %v, double * %ptr) nounwind {
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%val = load double* %ptr
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%i0 = insertelement <4 x double> zeroinitializer, double %val, i32 0
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ret <4 x double> %i0
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}
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; CHECK: vmovaps %ymm
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define void @storev16i16(<16 x i16> %a) nounwind {
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store <16 x i16> %a, <16 x i16>* undef, align 32
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unreachable
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}
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; CHECK: vmovups %ymm
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define void @storev16i16_01(<16 x i16> %a) nounwind {
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store <16 x i16> %a, <16 x i16>* undef, align 4
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unreachable
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}
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; CHECK: vmovaps %ymm
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define void @storev32i8(<32 x i8> %a) nounwind {
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store <32 x i8> %a, <32 x i8>* undef, align 32
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unreachable
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}
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; CHECK: vmovups %ymm
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define void @storev32i8_01(<32 x i8> %a) nounwind {
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store <32 x i8> %a, <32 x i8>* undef, align 4
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unreachable
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}
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; It is faster to make two saves, if the data is already in XMM registers. For
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; example, after making an integer operation.
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; CHECK: _double_save
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; CHECK-NOT: vinsertf128 $1
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; CHECK-NOT: vinsertf128 $0
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; CHECK: vmovaps %xmm
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; CHECK: vmovaps %xmm
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define void @double_save(<4 x i32> %A, <4 x i32> %B, <8 x i32>* %P) nounwind ssp {
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entry:
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%Z = shufflevector <4 x i32>%A, <4 x i32>%B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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store <8 x i32> %Z, <8 x i32>* %P, align 16
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ret void
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}
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declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) nounwind
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; CHECK_O0: _f_f
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; CHECK-O0: vmovss LCPI
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; CHECK-O0: vxorps %xmm
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; CHECK-O0: vmovss %xmm
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define void @f_f() nounwind {
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allocas:
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br i1 undef, label %cif_mask_all, label %cif_mask_mixed
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cif_mask_all: ; preds = %allocas
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unreachable
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cif_mask_mixed: ; preds = %allocas
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br i1 undef, label %cif_mixed_test_all, label %cif_mixed_test_any_check
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cif_mixed_test_all: ; preds = %cif_mask_mixed
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call void @llvm.x86.avx.maskstore.ps.256(i8* undef, <8 x float> <float 0xFFFFFFFFE0000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, <8 x float> undef) nounwind
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unreachable
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cif_mixed_test_any_check: ; preds = %cif_mask_mixed
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unreachable
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}
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