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a7879dcf33
llvm-6502/lib/Target/R600
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Michel Danzer a7879dcf33 R600/SI: Also enable WQM for image opcodes which calculate LOD v3 
If whole quad mode isn't enabled for these, the level of detail is
calculated incorrectly for pixels along diagonal triangle edges, causing
artifacts.

v2: Use a TSFlag instead of lots of switch cases
v3: Add test coverage

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642
Reviewed-by: Tom Stellard <tom@stellard.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228372 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-06 02:51:20 +00:00
..
AsmParser R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
InstPrinter [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
MCTargetDesc Add r224985 back with fixes. 2015-01-19 21:11:14 +00:00
TargetInfo R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPU.h [PM] Remove a bunch of stale TTI creation method declarations. I nuked 2015-02-01 00:22:15 +00:00
AMDGPU.td R600/SI: Add subtarget feature for if f32 fma is fast 2015-01-29 19:34:25 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAsmPrinter.cpp Compute the ELF SectionKind from the flags. 2015-01-29 17:33:21 +00:00
AMDGPUAsmPrinter.h std::unique_ptrify the MCStreamer argument to createAsmPrinter 2015-01-18 20:29:04 +00:00
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
AMDGPUInstrInfo.h R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2 2015-02-03 17:37:57 +00:00
AMDGPUInstrInfo.td R600/SI: Add class intrinsic 2015-01-06 23:00:37 +00:00
AMDGPUInstructions.td R600/SI: Only select cvt_flr/cvt_rpi with no NaNs. 2015-01-31 21:28:13 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp R600: Don't promote i64 stores to v2i32 during DAG legalization 2015-02-04 20:49:49 +00:00
AMDGPUISelLowering.cpp R600/SI: Make more store operations legal 2015-02-04 20:49:51 +00:00
AMDGPUISelLowering.h Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
AMDGPUMCInstLower.h R600/SI: Don't shrink instructions whose e32 encoding doesn't exist 2015-01-15 18:42:51 +00:00
AMDGPUPromoteAlloca.cpp
AMDGPURegisterInfo.cpp R600/SI: Enable inline assembly 2014-12-03 04:08:00 +00:00
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
AMDGPUSubtarget.h R600/SI: Enable subreg liveness by default 2015-02-04 23:14:18 +00:00
AMDGPUTargetMachine.cpp [multiversion] Switch all of the targets over to use the 2015-02-01 13:20:00 +00:00
AMDGPUTargetMachine.h [multiversion] Switch all of the targets over to use the 2015-02-01 13:20:00 +00:00
AMDGPUTargetTransformInfo.cpp R600/SI: Fix bug in TTI loop unrolling preferences 2015-02-05 15:32:18 +00:00
AMDGPUTargetTransformInfo.h [multiversion] Remove the function parameter from the unrolling 2015-02-01 14:31:23 +00:00
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
CaymanInstructions.td Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
CIInstructions.td Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
CMakeLists.txt R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
EvergreenInstructions.td Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
LLVMBuild.txt
Makefile
Processors.td R600/SI: Add subtarget feature for if f32 fma is fast 2015-01-29 19:34:25 +00:00
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
R600Intrinsics.td
R600ISelLowering.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
R600ISelLowering.h Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
SIAnnotateControlFlow.cpp R600/SI: Fix bug from insertion of llvm.SI.end.cf into loop headers 2015-02-05 15:32:15 +00:00
SIDefines.h R600/SI: Also enable WQM for image opcodes which calculate LOD v3 2015-02-06 02:51:20 +00:00
SIFixSGPRCopies.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIFixSGPRLiveRanges.cpp
SIFoldOperands.cpp Fix typo 2015-01-31 23:37:27 +00:00
SIInsertWaits.cpp R600/SI: Fix dependency between instruction writing M0 and S_SENDMSG on VI (v2) 2015-02-03 17:37:52 +00:00
SIInstrFormats.td R600/SI: Also enable WQM for image opcodes which calculate LOD v3 2015-02-06 02:51:20 +00:00
SIInstrInfo.cpp R600/SI: Fix B64 VALU shifts on VI 2015-02-03 21:53:01 +00:00
SIInstrInfo.h R600/SI: Also enable WQM for image opcodes which calculate LOD v3 2015-02-06 02:51:20 +00:00
SIInstrInfo.td R600/SI: Also enable WQM for image opcodes which calculate LOD v3 2015-02-06 02:51:20 +00:00
SIInstructions.td R600/SI: Also enable WQM for image opcodes which calculate LOD v3 2015-02-06 02:51:20 +00:00
SIIntrinsics.td
SIISelLowering.cpp R600/SI: Expand misaligned 16-bit memory accesses 2015-02-04 20:49:52 +00:00
SIISelLowering.h Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
SILoadStoreOptimizer.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
SILowerControlFlow.cpp R600/SI: Also enable WQM for image opcodes which calculate LOD v3 2015-02-06 02:51:20 +00:00
SILowerI1Copies.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIMachineFunctionInfo.cpp R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
SIMachineFunctionInfo.h R600/SI: Add subtarget feature to enable VGPR spilling for all shader types 2015-01-20 19:33:04 +00:00
SIPrepareScratchRegs.cpp R600/SI: Fix simple-loop.ll test 2015-01-20 19:33:02 +00:00
SIRegisterInfo.cpp R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2 2015-02-03 17:37:57 +00:00
SIRegisterInfo.h R600/SI: Define a schedule model and enable the generic machine scheduler 2015-01-29 16:55:25 +00:00
SIRegisterInfo.td R600/SI: Use RegisterOperands to specify which operands can accept immediates 2015-01-12 19:33:18 +00:00
SISchedule.td R600/SI: Define a schedule model 2015-01-14 01:13:19 +00:00
SIShrinkInstructions.cpp R600/SI: Don't shrink instructions whose e32 encoding doesn't exist 2015-01-15 18:42:51 +00:00
SITypeRewriter.cpp
VIInstrFormats.td R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
VIInstructions.td R600/SI: Add VI versions of MUBUF loads and stores 2015-01-27 17:24:58 +00:00