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a7a5854f1c
can in 32-bit mode we can choose to optionally *use* 64-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
2.7 KiB
C++
80 lines
2.7 KiB
C++
//=====-- PPCSubtarget.h - Define Subtarget for the PPC -------*- C++ -*--====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Nate Begeman and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPCSUBTARGET_H
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#define POWERPCSUBTARGET_H
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#include "llvm/Target/TargetInstrItineraries.h"
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#include "llvm/Target/TargetSubtarget.h"
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#include <string>
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namespace llvm {
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class Module;
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class PPCSubtarget : public TargetSubtarget {
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protected:
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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unsigned StackAlignment;
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/// Selected instruction itineraries (one entry per itinerary class.)
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InstrItineraryData InstrItins;
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/// Used by the ISel to turn in optimizations for POWER4-derived architectures
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bool IsGigaProcessor;
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bool Has64BitSupport;
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bool Use64BitRegs;
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bool HasAltivec;
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bool HasFSQRT;
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bool HasSTFIWX;
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bool IsAIX;
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bool IsDarwin;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified module.
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///
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PPCSubtarget(const Module &M, const std::string &FS, bool is64Bit);
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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unsigned getStackAlignment() const { return StackAlignment; }
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/// getInstrItins - Return the instruction itineraies based on subtarget
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/// selection.
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const InstrItineraryData getInstrItineraryData() const { return InstrItins; }
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const char *getTargetDataString() const {
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// FIXME: Make is64Bit be for the processor, not the target.
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return true ? "E-p:32:32-d:32-l:32" : "E-p:64:64-d:32-l:32";
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}
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bool hasFSQRT() const { return HasFSQRT; }
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bool hasSTFIWX() const { return HasSTFIWX; }
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bool use64BitRegs() const { return Use64BitRegs; }
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bool hasAltivec() const { return HasAltivec; }
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bool isAIX() const { return IsAIX; }
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bool isDarwin() const { return IsDarwin; }
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bool has64BitSupport() const { return Has64BitSupport; }
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bool isGigaProcessor() const { return IsGigaProcessor; }
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};
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} // End llvm namespace
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#endif
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