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callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
83 lines
1.9 KiB
LLVM
83 lines
1.9 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
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define i32 @t0(i1 zeroext %a) nounwind {
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%1 = zext i1 %a to i32
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ret i32 %1
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}
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define i32 @t1(i8 signext %a) nounwind {
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%1 = sext i8 %a to i32
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ret i32 %1
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}
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define i32 @t2(i8 zeroext %a) nounwind {
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%1 = zext i8 %a to i32
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ret i32 %1
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}
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define i32 @t3(i16 signext %a) nounwind {
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%1 = sext i16 %a to i32
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ret i32 %1
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}
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define i32 @t4(i16 zeroext %a) nounwind {
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%1 = zext i16 %a to i32
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ret i32 %1
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}
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define void @foo(i8 %a, i16 %b) nounwind {
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; ARM: foo
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; THUMB: foo
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;; Materialize i1 1
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; ARM: movw r2, #1
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;; zero-ext
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; ARM: and r2, r2, #1
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; THUMB: and r2, r2, #1
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%1 = call i32 @t0(i1 zeroext 1)
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; ARM: sxtb r2, r1
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; ARM: mov r0, r2
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; THUMB: sxtb r2, r1
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; THUMB: mov r0, r2
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%2 = call i32 @t1(i8 signext %a)
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; ARM: uxtb r2, r1
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; ARM: mov r0, r2
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; THUMB: uxtb r2, r1
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; THUMB: mov r0, r2
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%3 = call i32 @t2(i8 zeroext %a)
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; ARM: sxth r2, r1
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; ARM: mov r0, r2
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; THUMB: sxth r2, r1
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; THUMB: mov r0, r2
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%4 = call i32 @t3(i16 signext %b)
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; ARM: uxth r2, r1
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; ARM: mov r0, r2
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; THUMB: uxth r2, r1
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; THUMB: mov r0, r2
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%5 = call i32 @t4(i16 zeroext %b)
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;; A few test to check materialization
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;; Note: i1 1 was materialized with t1 call
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; ARM: movw r1, #255
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%6 = call i32 @t2(i8 zeroext 255)
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; ARM: movw r1, #65535
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; THUMB: movw r1, #65535
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%7 = call i32 @t4(i16 zeroext 65535)
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ret void
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}
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define void @foo2() nounwind {
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%1 = call signext i16 @t5()
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%2 = call zeroext i16 @t6()
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%3 = call signext i8 @t7()
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%4 = call zeroext i8 @t8()
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%5 = call zeroext i1 @t9()
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ret void
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}
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declare signext i16 @t5();
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declare zeroext i16 @t6();
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declare signext i8 @t7();
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declare zeroext i8 @t8();
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declare zeroext i1 @t9();
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