mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-11 08:07:22 +00:00
f99c1e5a19
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146100 91177308-0d34-0410-b5e6-96231b3b80d8
307 lines
11 KiB
TableGen
307 lines
11 KiB
TableGen
//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the MIPS register file
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//===----------------------------------------------------------------------===//
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let Namespace = "Mips" in {
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def sub_fpeven : SubRegIndex;
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def sub_fpodd : SubRegIndex;
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def sub_32 : SubRegIndex;
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}
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// We have banks of 32 registers each.
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class MipsReg<string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "Mips";
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}
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class MipsRegWithSubRegs<string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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field bits<5> Num;
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let Namespace = "Mips";
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}
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// Mips CPU Registers
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class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
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let Num = num;
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}
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// Mips 64-bit CPU Registers
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class Mips64GPRReg<bits<5> num, string n, list<Register> subregs>
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: MipsRegWithSubRegs<n, subregs> {
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let Num = num;
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let SubRegIndices = [sub_32];
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}
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// Mips 32-bit FPU Registers
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class FPR<bits<5> num, string n> : MipsReg<n> {
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let Num = num;
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}
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// Mips 64-bit (aliased) FPU Registers
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class AFPR<bits<5> num, string n, list<Register> subregs>
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: MipsRegWithSubRegs<n, subregs> {
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let Num = num;
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let SubRegIndices = [sub_fpeven, sub_fpodd];
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}
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class AFPR64<bits<5> num, string n, list<Register> subregs>
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: MipsRegWithSubRegs<n, subregs> {
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let Num = num;
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let SubRegIndices = [sub_32];
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}
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// Mips Hardware Registers
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class HWR<bits<5> num, string n> : MipsReg<n> {
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let Num = num;
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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let Namespace = "Mips" in {
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// FIXME: Fix DwarfRegNum.
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// General Purpose Registers
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def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
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def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
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def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
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def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
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def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
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def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
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def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
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def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
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def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
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def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
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def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
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def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
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def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
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def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
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def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
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def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
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def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
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def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
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def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
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def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
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def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
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def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
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def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
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def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
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def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
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def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
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def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
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def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
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def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
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def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
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def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
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def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
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// General Purpose 64-bit Registers
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def ZERO_64 : Mips64GPRReg< 0, "ZERO", [ZERO]>;
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def AT_64 : Mips64GPRReg< 1, "AT", [AT]>;
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def V0_64 : Mips64GPRReg< 2, "2", [V0]>;
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def V1_64 : Mips64GPRReg< 3, "3", [V1]>;
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def A0_64 : Mips64GPRReg< 4, "4", [A0]>;
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def A1_64 : Mips64GPRReg< 5, "5", [A1]>;
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def A2_64 : Mips64GPRReg< 6, "6", [A2]>;
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def A3_64 : Mips64GPRReg< 7, "7", [A3]>;
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def T0_64 : Mips64GPRReg< 8, "8", [T0]>;
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def T1_64 : Mips64GPRReg< 9, "9", [T1]>;
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def T2_64 : Mips64GPRReg< 10, "10", [T2]>;
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def T3_64 : Mips64GPRReg< 11, "11", [T3]>;
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def T4_64 : Mips64GPRReg< 12, "12", [T4]>;
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def T5_64 : Mips64GPRReg< 13, "13", [T5]>;
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def T6_64 : Mips64GPRReg< 14, "14", [T6]>;
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def T7_64 : Mips64GPRReg< 15, "15", [T7]>;
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def S0_64 : Mips64GPRReg< 16, "16", [S0]>;
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def S1_64 : Mips64GPRReg< 17, "17", [S1]>;
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def S2_64 : Mips64GPRReg< 18, "18", [S2]>;
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def S3_64 : Mips64GPRReg< 19, "19", [S3]>;
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def S4_64 : Mips64GPRReg< 20, "20", [S4]>;
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def S5_64 : Mips64GPRReg< 21, "21", [S5]>;
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def S6_64 : Mips64GPRReg< 22, "22", [S6]>;
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def S7_64 : Mips64GPRReg< 23, "23", [S7]>;
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def T8_64 : Mips64GPRReg< 24, "24", [T8]>;
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def T9_64 : Mips64GPRReg< 25, "25", [T9]>;
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def K0_64 : Mips64GPRReg< 26, "26", [K0]>;
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def K1_64 : Mips64GPRReg< 27, "27", [K1]>;
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def GP_64 : Mips64GPRReg< 28, "GP", [GP]>;
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def SP_64 : Mips64GPRReg< 29, "SP", [SP]>;
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def FP_64 : Mips64GPRReg< 30, "FP", [FP]>;
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def RA_64 : Mips64GPRReg< 31, "RA", [RA]>;
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/// Mips Single point precision FPU Registers
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def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
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def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
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def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>;
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def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>;
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def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>;
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def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>;
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def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>;
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def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>;
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def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>;
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def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>;
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def F10 : FPR<10, "F10">, DwarfRegNum<[42]>;
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def F11 : FPR<11, "F11">, DwarfRegNum<[43]>;
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def F12 : FPR<12, "F12">, DwarfRegNum<[44]>;
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def F13 : FPR<13, "F13">, DwarfRegNum<[45]>;
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def F14 : FPR<14, "F14">, DwarfRegNum<[46]>;
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def F15 : FPR<15, "F15">, DwarfRegNum<[47]>;
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def F16 : FPR<16, "F16">, DwarfRegNum<[48]>;
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def F17 : FPR<17, "F17">, DwarfRegNum<[49]>;
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def F18 : FPR<18, "F18">, DwarfRegNum<[50]>;
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def F19 : FPR<19, "F19">, DwarfRegNum<[51]>;
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def F20 : FPR<20, "F20">, DwarfRegNum<[52]>;
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def F21 : FPR<21, "F21">, DwarfRegNum<[53]>;
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def F22 : FPR<22, "F22">, DwarfRegNum<[54]>;
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def F23 : FPR<23, "F23">, DwarfRegNum<[55]>;
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def F24 : FPR<24, "F24">, DwarfRegNum<[56]>;
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def F25 : FPR<25, "F25">, DwarfRegNum<[57]>;
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def F26 : FPR<26, "F26">, DwarfRegNum<[58]>;
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def F27 : FPR<27, "F27">, DwarfRegNum<[59]>;
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def F28 : FPR<28, "F28">, DwarfRegNum<[60]>;
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def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
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def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
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def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
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/// Mips Double point precision FPU Registers (aliased
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/// with the single precision to hold 64 bit values)
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def D0 : AFPR< 0, "F0", [F0, F1]>;
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def D1 : AFPR< 2, "F2", [F2, F3]>;
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def D2 : AFPR< 4, "F4", [F4, F5]>;
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def D3 : AFPR< 6, "F6", [F6, F7]>;
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def D4 : AFPR< 8, "F8", [F8, F9]>;
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def D5 : AFPR<10, "F10", [F10, F11]>;
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def D6 : AFPR<12, "F12", [F12, F13]>;
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def D7 : AFPR<14, "F14", [F14, F15]>;
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def D8 : AFPR<16, "F16", [F16, F17]>;
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def D9 : AFPR<18, "F18", [F18, F19]>;
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def D10 : AFPR<20, "F20", [F20, F21]>;
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def D11 : AFPR<22, "F22", [F22, F23]>;
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def D12 : AFPR<24, "F24", [F24, F25]>;
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def D13 : AFPR<26, "F26", [F26, F27]>;
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def D14 : AFPR<28, "F28", [F28, F29]>;
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def D15 : AFPR<30, "F30", [F30, F31]>;
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/// Mips Double point precision FPU Registers in MFP64 mode.
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def D0_64 : AFPR64<0, "F0", [F0]>;
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def D1_64 : AFPR64<1, "F1", [F1]>;
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def D2_64 : AFPR64<2, "F2", [F2]>;
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def D3_64 : AFPR64<3, "F3", [F3]>;
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def D4_64 : AFPR64<4, "F4", [F4]>;
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def D5_64 : AFPR64<5, "F5", [F5]>;
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def D6_64 : AFPR64<6, "F6", [F6]>;
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def D7_64 : AFPR64<7, "F7", [F7]>;
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def D8_64 : AFPR64<8, "F8", [F8]>;
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def D9_64 : AFPR64<9, "F9", [F9]>;
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def D10_64 : AFPR64<10, "F10", [F10]>;
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def D11_64 : AFPR64<11, "F11", [F11]>;
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def D12_64 : AFPR64<12, "F12", [F12]>;
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def D13_64 : AFPR64<13, "F13", [F13]>;
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def D14_64 : AFPR64<14, "F14", [F14]>;
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def D15_64 : AFPR64<15, "F15", [F15]>;
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def D16_64 : AFPR64<16, "F16", [F16]>;
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def D17_64 : AFPR64<17, "F17", [F17]>;
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def D18_64 : AFPR64<18, "F18", [F18]>;
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def D19_64 : AFPR64<19, "F19", [F19]>;
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def D20_64 : AFPR64<20, "F20", [F20]>;
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def D21_64 : AFPR64<21, "F21", [F21]>;
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def D22_64 : AFPR64<22, "F22", [F22]>;
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def D23_64 : AFPR64<23, "F23", [F23]>;
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def D24_64 : AFPR64<24, "F24", [F24]>;
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def D25_64 : AFPR64<25, "F25", [F25]>;
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def D26_64 : AFPR64<26, "F26", [F26]>;
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def D27_64 : AFPR64<27, "F27", [F27]>;
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def D28_64 : AFPR64<28, "F28", [F28]>;
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def D29_64 : AFPR64<29, "F29", [F29]>;
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def D30_64 : AFPR64<30, "F30", [F30]>;
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def D31_64 : AFPR64<31, "F31", [F31]>;
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// Hi/Lo registers
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def HI : Register<"hi">, DwarfRegNum<[64]>;
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def LO : Register<"lo">, DwarfRegNum<[65]>;
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let SubRegIndices = [sub_32] in {
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def HI64 : RegisterWithSubRegs<"hi", [HI]>;
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def LO64 : RegisterWithSubRegs<"lo", [LO]>;
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}
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// Status flags register
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def FCR31 : Register<"31">;
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// Hardware register $29
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def HWR29 : Register<"29">;
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def HWR29_64 : Register<"29">;
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}
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//===----------------------------------------------------------------------===//
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// Register Classes
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//===----------------------------------------------------------------------===//
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def CPURegs : RegisterClass<"Mips", [i32], 32, (add
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// Return Values and Arguments
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V0, V1, A0, A1, A2, A3,
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// Not preserved across procedure calls
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T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
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// Callee save
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S0, S1, S2, S3, S4, S5, S6, S7,
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// Reserved
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ZERO, AT, K0, K1, GP, SP, FP, RA)>;
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def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add
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// Return Values and Arguments
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V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
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// Not preserved across procedure calls
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T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, T8_64, T9_64,
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// Callee save
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S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
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// Reserved
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ZERO_64, AT_64, K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)> {
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let SubRegClasses = [(CPURegs sub_32)];
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}
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// 64bit fp:
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// * FGR64 - 32 64-bit registers
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// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
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//
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// 32bit fp:
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// * FGR32 - 16 32-bit even registers
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// * FGR32 - 32 32-bit registers (single float only mode)
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def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
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def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
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// Return Values and Arguments
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D0, D1, D6, D7,
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// Not preserved across procedure calls
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D2, D3, D4, D5, D8, D9,
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// Callee save
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D10, D11, D12, D13, D14, D15)> {
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let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
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}
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def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> {
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let SubRegClasses = [(FGR32 sub_32)];
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}
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// Condition Register for floating point operations
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def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>;
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// Hi/Lo Registers
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def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>;
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def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)> {
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let SubRegClasses = [(HILO sub_32)];
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}
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// Hardware registers
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def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;
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def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>;
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