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and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
158 lines
5.5 KiB
C++
158 lines
5.5 KiB
C++
//===-- CodeGen/MachineInstBuilder.h - Simplify creation of MIs -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file exposes a function named BuildMI, which is useful for dramatically
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// simplifying how MachineInstr's are created. It allows use of code like this:
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//
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// M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2);
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
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#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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namespace llvm {
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class TargetInstrDesc;
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class MachineInstrBuilder {
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MachineInstr *MI;
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public:
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explicit MachineInstrBuilder(MachineInstr *mi) : MI(mi) {}
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/// Allow automatic conversion to the machine instruction we are working on.
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///
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operator MachineInstr*() const { return MI; }
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operator MachineBasicBlock::iterator() const { return MI; }
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/// addReg - Add a new virtual register operand...
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///
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const
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MachineInstrBuilder &addReg(unsigned RegNo, bool isDef = false,
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bool isImp = false, bool isKill = false,
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bool isDead = false, unsigned SubReg = 0) const {
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MI->addOperand(MachineOperand::CreateReg(RegNo, isDef, isImp, isKill,
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isDead, SubReg));
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return *this;
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}
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/// addImm - Add a new immediate operand.
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///
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const MachineInstrBuilder &addImm(int64_t Val) const {
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MI->addOperand(MachineOperand::CreateImm(Val));
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return *this;
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}
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const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
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MI->addOperand(MachineOperand::CreateFPImm(Val));
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return *this;
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}
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const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB) const {
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MI->addOperand(MachineOperand::CreateMBB(MBB));
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return *this;
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}
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const MachineInstrBuilder &addFrameIndex(unsigned Idx) const {
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MI->addOperand(MachineOperand::CreateFI(Idx));
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return *this;
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}
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const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx,
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int Offset = 0) const {
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MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
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return *this;
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}
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const MachineInstrBuilder &addJumpTableIndex(unsigned Idx) const {
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MI->addOperand(MachineOperand::CreateJTI(Idx));
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return *this;
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}
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const MachineInstrBuilder &addGlobalAddress(GlobalValue *GV,
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int64_t Offset = 0) const {
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MI->addOperand(MachineOperand::CreateGA(GV, Offset));
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return *this;
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}
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const MachineInstrBuilder &addExternalSymbol(const char *FnName,
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int64_t Offset = 0) const {
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MI->addOperand(MachineOperand::CreateES(FnName, Offset));
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return *this;
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}
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};
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/// BuildMI - Builder interface. Specify how to create the initial instruction
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/// itself.
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///
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inline MachineInstrBuilder BuildMI(MachineFunction &MF,
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const TargetInstrDesc &TID) {
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return MachineInstrBuilder(MF.CreateMachineInstr(TID));
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}
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/// BuildMI - This version of the builder sets up the first operand as a
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/// destination virtual register.
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///
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inline MachineInstrBuilder BuildMI(MachineFunction &MF,
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const TargetInstrDesc &TID,
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unsigned DestReg) {
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return MachineInstrBuilder(MF.CreateMachineInstr(TID)).addReg(DestReg, true);
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}
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/// BuildMI - This version of the builder inserts the newly-built
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/// instruction before the given position in the given MachineBasicBlock, and
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/// sets up the first operand as a destination virtual register.
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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const TargetInstrDesc &TID,
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unsigned DestReg) {
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MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID);
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BB.insert(I, MI);
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return MachineInstrBuilder(MI).addReg(DestReg, true);
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}
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/// BuildMI - This version of the builder inserts the newly-built
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/// instruction before the given position in the given MachineBasicBlock, and
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/// does NOT take a destination register.
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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const TargetInstrDesc &TID) {
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MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID);
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BB.insert(I, MI);
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return MachineInstrBuilder(MI);
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}
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/// BuildMI - This version of the builder inserts the newly-built
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/// instruction at the end of the given MachineBasicBlock, and does NOT take a
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/// destination register.
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
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const TargetInstrDesc &TID) {
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return BuildMI(*BB, BB->end(), TID);
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}
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/// BuildMI - This version of the builder inserts the newly-built
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/// instruction at the end of the given MachineBasicBlock, and sets up the first
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/// operand as a destination virtual register.
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
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const TargetInstrDesc &TID,
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unsigned DestReg) {
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return BuildMI(*BB, BB->end(), TID, DestReg);
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}
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} // End llvm namespace
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#endif
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