llvm-6502/test/CodeGen/ARM/sub-cmp-peephole.ll
Manman Ren 540cda34b0 ARM: update peephole optimization.
More condition codes are included when deciding whether to remove cmp after
a sub instruction. Specifically, we extend from GE|LT|GT|LE to 
GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we
should be able to replace with "sub a, b; movls".

rdar: 11725965


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25 21:49:38 +00:00

47 lines
931 B
LLVM

; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
define i32 @f(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: f:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, %b
%sub = sub nsw i32 %a, %b
%sub. = select i1 %cmp, i32 %sub, i32 0
ret i32 %sub.
}
define i32 @g(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: g:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp slt i32 %a, %b
%sub = sub nsw i32 %b, %a
%sub. = select i1 %cmp, i32 %sub, i32 0
ret i32 %sub.
}
define i32 @h(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: h:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, 3
%sub = sub nsw i32 %a, 3
%sub. = select i1 %cmp, i32 %sub, i32 %b
ret i32 %sub.
}
; rdar://11725965
define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK: i:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp ult i32 %a, %b
%sub = sub i32 %b, %a
%sub. = select i1 %cmp, i32 %sub, i32 0
ret i32 %sub.
}