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b0cf29c5cf
the comments in FastISelEmitter.cpp for details on what this is. This is currently experimental and unusable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54751 91177308-0d34-0410-b5e6-96231b3b80d8
363 lines
12 KiB
C++
363 lines
12 KiB
C++
//===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits a "fast" instruction selector.
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//
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// This instruction selection method is designed to emit very poor code
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// quickly. Also, it is not designed to do much lowering, so most illegal
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// types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not
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// supported and cannot easily be added. Blocks containing operations
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// that are not supported need to be handled by a more capable selector,
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// such as the SelectionDAG selector.
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//
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// The intended use for "fast" instruction selection is "-O0" mode
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// compilation, where the quality of the generated code is irrelevant when
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// weighed against the speed at which the code can be generated.
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//
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// If compile time is so important, you might wonder why we don't just
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// skip codegen all-together, emit LLVM bytecode files, and execute them
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// with an interpreter. The answer is that it would complicate linking and
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// debugging, and also because that isn't how a compiler is expected to
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// work in some circles.
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//
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// If you need better generated code or more lowering than what this
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// instruction selector provides, use the SelectionDAG (DAGISel) instruction
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// selector instead. If you're looking here because SelectionDAG isn't fast
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// enough, consider looking into improving the SelectionDAG infastructure
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// instead. At the time of this writing there remain several major
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// opportunities for improvement.
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//
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//===----------------------------------------------------------------------===//
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#include "FastISelEmitter.h"
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#include "Record.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Streams.h"
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#include "llvm/ADT/VectorExtras.h"
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using namespace llvm;
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namespace {
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struct OperandsSignature {
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std::vector<std::string> Operands;
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bool operator<(const OperandsSignature &O) const {
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return Operands < O.Operands;
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}
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bool empty() const { return Operands.empty(); }
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void PrintParameters(std::ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i] == "r") {
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OS << "unsigned Op" << i;
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} else {
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assert("Unknown operand kind!");
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abort();
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}
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if (i + 1 != e)
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OS << ", ";
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}
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}
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void PrintArguments(std::ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i] == "r") {
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OS << "Op" << i;
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} else {
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assert("Unknown operand kind!");
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abort();
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}
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if (i + 1 != e)
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OS << ", ";
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}
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}
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void PrintManglingSuffix(std::ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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OS << Operands[i];
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}
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}
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};
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struct InstructionMemo {
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std::string Name;
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const CodeGenRegisterClass *RC;
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};
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}
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static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
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return CGP.getSDNodeInfo(Op).getEnumName();
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}
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static std::string getLegalCName(std::string OpName) {
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std::string::size_type pos = OpName.find("::");
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if (pos != std::string::npos)
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OpName.replace(pos, 2, "_");
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return OpName;
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}
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void FastISelEmitter::run(std::ostream &OS) {
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EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
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CGP.getTargetInfo().getName() + " target", OS);
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const CodeGenTarget &Target = CGP.getTargetInfo();
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// Get the namespace to insert instructions into. Make sure not to pick up
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// "TargetInstrInfo" by accidentally getting the namespace off the PHI
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// instruction or something.
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std::string InstNS;
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for (CodeGenTarget::inst_iterator i = Target.inst_begin(),
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e = Target.inst_end(); i != e; ++i) {
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InstNS = i->second.Namespace;
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if (InstNS != "TargetInstrInfo")
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break;
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}
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OS << "namespace llvm {\n";
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OS << "namespace " << InstNS << " {\n";
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OS << "class FastISel;\n";
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OS << "}\n";
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OS << "}\n";
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OS << "\n";
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if (!InstNS.empty()) InstNS += "::";
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typedef std::map<MVT::SimpleValueType, InstructionMemo> TypeMap;
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typedef std::map<std::string, TypeMap> OpcodeTypeMap;
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typedef std::map<OperandsSignature, OpcodeTypeMap> OperandsOpcodeTypeMap;
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OperandsOpcodeTypeMap SimplePatterns;
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// Create the supported type signatures.
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OperandsSignature KnownOperands;
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SimplePatterns[KnownOperands] = OpcodeTypeMap();
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KnownOperands.Operands.push_back("r");
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SimplePatterns[KnownOperands] = OpcodeTypeMap();
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KnownOperands.Operands.push_back("r");
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SimplePatterns[KnownOperands] = OpcodeTypeMap();
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for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
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E = CGP.ptm_end(); I != E; ++I) {
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const PatternToMatch &Pattern = *I;
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// For now, just look at Instructions, so that we don't have to worry
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// about emitting multiple instructions for a pattern.
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TreePatternNode *Dst = Pattern.getDstPattern();
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if (Dst->isLeaf()) continue;
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Record *Op = Dst->getOperator();
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if (!Op->isSubClassOf("Instruction"))
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continue;
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CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
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if (II.OperandList.empty())
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continue;
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Record *Op0Rec = II.OperandList[0].Rec;
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if (!Op0Rec->isSubClassOf("RegisterClass"))
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continue;
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const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
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if (!DstRC)
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continue;
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// Inspect the pattern.
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TreePatternNode *InstPatNode = Pattern.getSrcPattern();
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if (!InstPatNode) continue;
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if (InstPatNode->isLeaf()) continue;
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Record *InstPatOp = InstPatNode->getOperator();
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std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
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MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
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// For now, filter out instructions which just set a register to
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// an Operand, like MOV32ri.
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if (InstPatOp->isSubClassOf("Operand"))
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continue;
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// Check all the operands. For now only accept register operands.
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OperandsSignature Operands;
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for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
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TreePatternNode *Op = InstPatNode->getChild(i);
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if (!Op->isLeaf())
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goto continue_label;
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DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
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if (!OpDI)
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goto continue_label;
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Record *OpLeafRec = OpDI->getDef();
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if (!OpLeafRec->isSubClassOf("RegisterClass"))
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goto continue_label;
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const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
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if (!RC)
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goto continue_label;
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if (Op->getTypeNum(0) != VT)
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goto continue_label;
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Operands.Operands.push_back("r");
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}
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// If it's not a known signature, ignore it.
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if (!SimplePatterns.count(Operands))
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continue;
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// Ok, we found a pattern that we can handle. Remember it.
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{
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InstructionMemo Memo = { Pattern.getDstPattern()->getOperator()->getName(),
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DstRC };
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SimplePatterns[Operands][OpcodeName][VT] = Memo;
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}
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continue_label:;
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}
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OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
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OS << "\n";
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OS << "namespace llvm {\n";
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OS << "\n";
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// Declare the target FastISel class.
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OS << "class " << InstNS << "FastISel : public llvm::FastISel {\n";
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for (OperandsOpcodeTypeMap::const_iterator OI = SimplePatterns.begin(),
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OE = SimplePatterns.end(); OI != OE; ++OI) {
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const OperandsSignature &Operands = OI->first;
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const OpcodeTypeMap &OTM = OI->second;
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for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
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I != E; ++I) {
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const std::string &Opcode = I->first;
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const TypeMap &TM = I->second;
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for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
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TI != TE; ++TI) {
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MVT::SimpleValueType VT = TI->first;
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OS << " unsigned FastEmit_" << getLegalCName(Opcode)
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<< "_" << getLegalCName(getName(VT)) << "(";
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Operands.PrintParameters(OS);
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OS << ");\n";
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}
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OS << " unsigned FastEmit_" << getLegalCName(Opcode)
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<< "(MVT::SimpleValueType VT";
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if (!Operands.empty())
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OS << ", ";
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Operands.PrintParameters(OS);
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OS << ");\n";
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}
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OS << "unsigned FastEmit_";
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Operands.PrintManglingSuffix(OS);
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OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
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if (!Operands.empty())
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OS << ", ";
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Operands.PrintParameters(OS);
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OS << ");\n";
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}
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OS << "public:\n";
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OS << " FastISel(MachineBasicBlock *mbb, MachineFunction *mf, ";
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OS << "const TargetInstrInfo *tii) : llvm::FastISel(mbb, mf, tii) {}\n";
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OS << "};\n";
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OS << "\n";
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// Define the target FastISel creation function.
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OS << "llvm::FastISel *" << InstNS
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<< "createFastISel(MachineBasicBlock *mbb, MachineFunction *mf, ";
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OS << "const TargetInstrInfo *tii) {\n";
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OS << " return new " << InstNS << "FastISel(mbb, mf, tii);\n";
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OS << "}\n";
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OS << "\n";
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// Now emit code for all the patterns that we collected.
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for (OperandsOpcodeTypeMap::const_iterator OI = SimplePatterns.begin(),
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OE = SimplePatterns.end(); OI != OE; ++OI) {
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const OperandsSignature &Operands = OI->first;
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const OpcodeTypeMap &OTM = OI->second;
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for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
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I != E; ++I) {
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const std::string &Opcode = I->first;
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const TypeMap &TM = I->second;
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OS << "// FastEmit functions for " << Opcode << ".\n";
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OS << "\n";
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// Emit one function for each opcode,type pair.
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for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
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TI != TE; ++TI) {
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MVT::SimpleValueType VT = TI->first;
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const InstructionMemo &Memo = TI->second;
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OS << "unsigned " << InstNS << "FastISel::FastEmit_"
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<< getLegalCName(Opcode)
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<< "_" << getLegalCName(getName(VT)) << "(";
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Operands.PrintParameters(OS);
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OS << ") {\n";
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OS << " return FastEmitInst_";
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Operands.PrintManglingSuffix(OS);
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OS << "(" << InstNS << Memo.Name << ", ";
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OS << InstNS << Memo.RC->getName() << "RegisterClass";
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if (!Operands.empty())
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OS << ", ";
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Operands.PrintArguments(OS);
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OS << ");\n";
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OS << "}\n";
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OS << "\n";
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}
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// Emit one function for the opcode that demultiplexes based on the type.
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OS << "unsigned " << InstNS << "FastISel::FastEmit_"
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<< getLegalCName(Opcode) << "(MVT::SimpleValueType VT";
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if (!Operands.empty())
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OS << ", ";
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Operands.PrintParameters(OS);
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OS << ") {\n";
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OS << " switch (VT) {\n";
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for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
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TI != TE; ++TI) {
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MVT::SimpleValueType VT = TI->first;
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std::string TypeName = getName(VT);
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OS << " case " << TypeName << ": return FastEmit_"
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<< getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "(";
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Operands.PrintArguments(OS);
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OS << ");\n";
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}
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OS << " default: return 0;\n";
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OS << " }\n";
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OS << "}\n";
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OS << "\n";
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}
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// Emit one function for the operand signature that demultiplexes based
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// on opcode and type.
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OS << "unsigned " << InstNS << "FastISel::FastEmit_";
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Operands.PrintManglingSuffix(OS);
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OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
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if (!Operands.empty())
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OS << ", ";
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Operands.PrintParameters(OS);
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OS << ") {\n";
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OS << " switch (Opcode) {\n";
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for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
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I != E; ++I) {
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const std::string &Opcode = I->first;
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OS << " case " << Opcode << ": return FastEmit_"
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<< getLegalCName(Opcode) << "(VT";
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if (!Operands.empty())
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OS << ", ";
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Operands.PrintArguments(OS);
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OS << ");\n";
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}
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OS << " default: return 0;\n";
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OS << " }\n";
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OS << "}\n";
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OS << "\n";
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}
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OS << "}\n";
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}
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// todo: really filter out Constants
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