mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-13 21:05:16 +00:00
c24cb3551e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
185 lines
5.1 KiB
LLVM
185 lines
5.1 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vcges8:
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;CHECK: vcge.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = icmp sge <8 x i8> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vcges16:
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;CHECK: vcge.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = icmp sge <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vcges32:
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;CHECK: vcge.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = icmp sge <2 x i32> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vcgeu8:
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;CHECK: vcge.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = icmp uge <8 x i8> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vcgeu16:
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;CHECK: vcge.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = icmp uge <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vcgeu32:
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;CHECK: vcge.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = icmp uge <2 x i32> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vcgef32:
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;CHECK: vcge.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp oge <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vcgeQs8:
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;CHECK: vcge.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = icmp sge <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vcgeQs16:
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;CHECK: vcge.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = icmp sge <8 x i16> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vcgeQs32:
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;CHECK: vcge.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = icmp sge <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vcgeQu8:
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;CHECK: vcge.u8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = icmp uge <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vcgeQu16:
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;CHECK: vcge.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = icmp uge <8 x i16> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vcgeQu32:
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;CHECK: vcge.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = icmp uge <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vcgeQf32:
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;CHECK: vcge.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = fcmp oge <4 x float> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vacgef32:
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;CHECK: vacge.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vacged(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vacgeQf32:
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;CHECK: vacge.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x i32> %tmp3
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}
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declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone
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define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
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;CHECK: vcgei8Z:
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;CHECK-NOT: vmov
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;CHECK-NOT: vmvn
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;CHECK: vcge.s8
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%tmp1 = load <8 x i8>* %A
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%tmp3 = icmp sge <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
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;CHECK: vclei8Z:
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;CHECK-NOT: vmov
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;CHECK-NOT: vmvn
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;CHECK: vcle.s8
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%tmp1 = load <8 x i8>* %A
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%tmp3 = icmp sle <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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